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研究生:李谷桓
研究生(外文):Gu-Huan Li
論文名稱:兩級游標尺延遲線之時間數位轉換器
論文名稱(外文):A Two Level Vernier Delay Line Time-to-Digital Converter
指導教授:周懷樸
指導教授(外文):Hwai-Pwu Chou
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學門:工程學門
學類:核子工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:103
中文關鍵詞:時間數位轉換器游標尺延遲線
外文關鍵詞:Time-to-Digital ConverterVernier Delay LineTDCVDL
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  本研究為設計一個兩級游標尺延遲線之時間數位轉換器,解決單級游標尺延遲線會發生信號轉換時間過長的問題,同時減少元件數目。介於兩個脈衝信號之間的待測時間,經由控制電路分解為參考時脈週期的整數倍及非整數倍兩部份,整數倍交由計數器計算,非整數倍則送到兩級游標尺延遲線。由第一級游標尺延遲線得到較粗略的解析度(Tclk / 14),再將處理過的信號經由本研究所設計之新架構的介面電路傳送到第二級游標尺延遲線得到更精確的解析(Tclk / 196),最後由讀出電路將溫度計碼型式的輸出轉為二進位型式的輸出並做減法的運算,得到最後的結果。游標尺延遲線所使用的延遲元件由延線鎖相迴路來控制其偏壓,使得延遲元件能夠穩定提供電路所需的兩種延遲時間:Tclk / 14及Tclk.15 / 196。
  電路使用的製程是TSMC CMOS 0.18um 1P6M,由延遲元件之延遲時間、信號轉換時間及誤差分析的考量,選擇參考時脈的頻率為200MHz。經由模擬結果得知,信號轉換的時間小於5個參考時脈週期,最大可量測的時間為75ns。在時間的解析度修正為29.6ps的情形下,DNL介於-0.33LSB ~ +0.69LSB,INL介於+0.47LSB ~ -1.08LSB。
This paper describes the design of time-to-digital converter with two level Vernier delay line(VDL), which is used to solve the problem of long conversion time in single level VDL and reduce the elements. The time to be measured between two pulse signals is separated into integral period part and non-integral period parts by control circuit. Integral part is sent into counter, and non-integral parts are sent into the two level VDL. In the first VDL can get coarse resolution(Tclk/14), and the signals will be transferred to the second VDL by the new structure interface circuit. Fine resolution(Tclk/196)can be gotten in the second VDL. Finally, readout circuit converts thermal code to binary code and do the subtraction to get the final results. The bias voltages of delay elements in VDL are controlled by DLL, this makes delay elements can stably provide two delay time:Tclk / 14 and Tclk.15 / 196.
The circuit uses the process of TSMC CMOS 0.18um 1P6M. 200Mhz clock frequency is chosen by the consideration of delay time, conversion time, and error analysis. From the simulation results, the conversion time is smaller than 5 clock periods, the maximum time can be measured is 75ns. After the fine resolution is modified to 29.6ps, the DNL is within -0.33LSB ~ +0.69LSB,and INL is within +0.47LSB ~ +1.08LSB.
誌  謝 I
摘  要 II
Abstract III
目錄 IV
圖目錄 VIII
表目錄 XII

第1章 緒論 1
1-1 時間數位轉換器之簡介 1
1-2 研究動機及目的 3
第2章 文獻回顧 4
2-1 類比式時間數位轉換器 4
2-1.1 時間轉換電壓之時間數位轉換器 6
2-1.2 雙斜率時間數位轉換器 7
2-2 數位式時間數位轉換器 9
2-2.1 游標尺延遲線之時間數位轉換器 11
2-2.2 延遲鎖相迴路陣列 15
2-2.3 脈衝縮減延遲元件 18
第3章 電路設計 21
3-1 整體架構 22
3-1.1 時序圖 22
3-1.2 系統架構圖 24
3-1.3 規格設定 27
3-2 控制電路 28
3-2.1 運作方式及設計 28
3-2.2 正單相時脈電路 32
3-2.3 TSPC D型閂鎖及D型正反器之設計 33
3-2.4 四位元計數器之設計 36
3-3 游標尺延遲線及延遲鎖相迴路之設計 38
3-3.1 延遲元件之設計 39
3-3.2 延遲鎖相迴路之設計 41
3-3.3 延遲尺延遲元件之設計 46
3-3.4 介面電路的設計 47
3-4 讀出電路之設計 52
3-4.1 讀出電路之基本架構 52
3-4.2 溫度計碼解碼電路 53
3-4.3 減法器 56
第4章 電路佈局 59
4-1 控制電路 59
4-2 游標尺延遲線 63
4-3 延遲鎖相迴路 69
4-4 讀出電路 71
4-5 整體電路 73
第5章 電路模擬及分析 75
5-1 控制電路 75
5-1.1 D型閂鎖 76
5-1.2 D型正反器 77
5-1.3 四位元計數器 78
5-2 游標尺延遲元件 79
5-2.1 延遲元件之模擬 79
5-2.2 D型正反器之模擬結果 83
5-3 延遲鎖相迴路之模擬 84
5-4 讀出電路之模擬 86
5-4.1 溫度計碼解碼器之模擬 86
5-4.2 減法器之模擬 87
5-5 整體電路之模擬 88
第6章 結論與建議 93

參考文獻 97
附錄一:參考頻率及階數之選擇 99
附錄二:誤差分析 102
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