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研究生:李進府
研究生(外文):Chin-Fu Li
論文名稱:用直流電壓偵測來校正鏡像抑制接收機
論文名稱(外文):Calibration using DC-Detection Technique for Image Rejection
指導教授:陳俊才陳俊才引用關係黃柏鈞黃柏鈞引用關係
指導教授(外文):Jiunn-Tsair ChenPo-Chiun Huang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:43
中文關鍵詞:鏡像抑制接收機校正無線
外文關鍵詞:image-reject receivercalibrationwireless
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摘要

由於半導體製程、DSP技術的進步,造就了近幾年來無線通訊積體電路的盛行,同時也發展了各式各樣無線通訊的運用。在接收機的製作上,鏡像抑制接收機的架構經常用來解決因為降頻所造成的鏡像干擾。這個架構在理論上來講,能完全的抑制降頻所造成的鏡像訊號干擾,但因為製程的不確定性,使得接收機存在著相位與增益的不匹配,造成鏡像抑制效果有限,而一個好的IC佈局,大約能達到40dB的鏡像抑制比,若不額外使用濾波器,將無法滿足一般無線通訊系統對鏡像抑制比的要求。
本論文提出了一個名為直流電壓偵測的校正方法,用來改善鏡像抑制比的表現。此校正方法適合實現在類比電路上,校正時,並不需要類比數位轉換器,以減少校正時所需要消耗的額外功率。同時輸入一個單頻的鏡像訊號,在經過兩次降頻後,將鏡像訊號降至0的頻率,行成一個DC的電壓值,利用此電壓來校正相位與增益的不匹配,經由模擬,最後鏡像抑制比能達到70dB以上。即增益的不匹配在0.04%、相位的不匹配在0.02度之內。除了鏡像抑制比外,校正時所需要的時間,大約只需要100�酨,所需要額外的功率在亦在1mW以內。在電路的複雜度上,除了鏡像訊號產生器和調整相位與增益的電路外,需要一個比較器、開關器和直流電壓偵測器(數位電路)。
Abstract

The wireless communication integrated circuits design prevail in the last decade due to the advances of semiconductor process and DSP. Image-reject architectures are frequently applied to alleviate the image interference induced in dual frequency down conversion receivers. Ideally, image-reject receivers can achieve infinite image rejection ratio (IRR). Process variation, however, causes unpredictable phase and gain mismatches in signal path and degrades the corresponding IRR. Good layout planning, in general, can attain around 40 dB IRR, this is not sufficient to fulfill stringent system requirement without other filter used.

In this thesis, a novel calibration technique named DC Detection is proposed to improve IRR performance. The calibrated technique is used in analog domain avoiding power consumption of ADC. At start of calibration, an image signal is fed into the receiver, after dual frequency down conversion, lead out an output DC voltage to represent the degree of gain and phase mismatch of the receiver. Extensive simulation results indicate that the IRR performance can be improved from 25dB to 70 dB with small circuit overhead. The additional power and time consumed by calibration are less than 1mW and 100us, respectively.
參考文獻

[1] L.Der. and B. Razavi, ” A 2-GHz CMOS image-reject receiver with LMS calibration, ”IEEE J. Solid-State Circuits, vol. 35, No. 1, Jan.2003.

[2] R. Montemayor and B. Razavi, “A self-calibrating 900-MHz CMOS
image-reject receiver,” in Proc. Eur. Solid-State Circuits Conf. ( ESSCIRC) 2000

[3] Elmala, M.A.I. and Embabi, S.H.K.; “Calibration of phase and gain mismatches in Weaver image-reject receiver” IEEE J. Solid-State Circuits, Volume: 39 , Issue: 2 , Feb. 2004

[4] Jacques C. Rudell, et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications” IEEE J. Solid-State Circuits, VOL. 32, NO. 12, DECEMBER 1997

[5] Behzad Razavi, “RF Microelectronics”, Prentice-Hall, 1998.
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