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研究生:蔡俊安
研究生(外文):Chun-An Tsai
論文名稱:射頻發射器與接收器積體電路設計
論文名稱(外文):Radio Frequency Transmitter and Receiver Integrated Circuit Design
指導教授:劉萬榮吳 渝
指導教授(外文):Wan-Rone LiouAdam Yu Wu
學位類別:博士
校院名稱:國立臺灣海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:108
中文關鍵詞:射頻發射器接收器
外文關鍵詞:Radio FrequencyTransmitterReceiver
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本論文主要係設計一CMOS 射頻發射機與接收機前端電路。其中接收機電路包含了低雜訊放大器和降頻轉移混波器。而發射機電路則包含了功率放大器、昇頻轉移混波器和電壓控制振盪器。全部的射頻接收機與發射機系統電路係用台積電公司的高頻模型設計。 於射頻接收機研究方面,在低雜訊放大器電路上我們使用電感匹配、帶通濾波器和電容以達成節省在信號的路徑上之電力消耗,並達到低雜訊和高增益之效果。在混波器的研究方面, 我們將平方律的混波器及共源級輸出緩衝器整合在一起,其不只確定最佳化元件的大小,並達成減少全部電路功率的消耗,且提供高線性度的性能。在發射機研究方面,其中兩級差動功率放大器不僅得到足夠的輸出功率,並具有良好的線性度。而昇頻轉換混波器係用Gilbert種類的混波器,四相輸出的壓控振盪器則用以做為發射機的本地振盪器。本論文亦以0.18-μm CMOS 製程設計一個鎖相迴路,其可振盪出信號操作頻率高達5-GHz。最後我們設計一個電流控制電路,其經由不同的負載調整最佳化的輸出電流來解決電磁干擾的問題。
This dissertation presents the design of a CMOS RF transmitter and receiver front end. The receiver contains a low noise amplifier, a down conversion mixer, and a voltage control oscillator. While the transmitter consists of a power amplifier, an up conversion mixer, and a voltage control oscillator. All the components were designed with the TSMC CMOS high frequency models. These models were specially implemented for RF receiver and transmitter design. In receiver design, we used the inductance matching skill, band pass filter, and the DC isolation capacitance to improve the system performance. We could get less power loss along the signal path, lower overall noise, and higher gain in the low-noise amplifier circuit design. For mixer circuit design, a single square-law mixer and common source output buffer were implemented at the same time. The mixer design was focused in optimizing device size, decreasing the total circuit power consumption, and providing high linearity performance. For transmitter design, a two-stage differential power amplifier was implemented to obtain enough output power and good efficiency. A Gilbert-type mixer was used for up-conversion mixer. A local oscillator is implemented with a voltage control oscillator, and provides a quadrature output. A phase locked loop (PLL) was designed with 0.18-μm one-poly-six-metal (1P6M) TSMC CMOS process. It generated a clock signal and the operating frequency up to 5-GHz. Finally, a current control circuit was designed by varying the loads to adjust the optimum driver current. This design can help us to solve the electro-magnetic interference (EMI) problem.
Dedication I
Acknowledgements II
Abstract III
Contents VI

Chapter 1 Introduction 1
1-1 Background and Motivation 1
1-2 Thesis Organization 6

Chapter 2 RF CMOS Receiver 8
2-1 Introduction 8
2-2 Low Noise Amplifier 9
2-3 Down-Conversion Mixer 26
2-4 Conclusion 34

Chapter 3 RF CMOS Transmitter 37
3-1 Introduction 37
3-2 Power Amplifier 38
3-3 Up-Conversion Mixer 48
3-4 Voltage Control Oscillator 52
3-5 Conclusion 70

Chapter 4 RF CMOS Phase Locked Loop 73
4-1 Introduction 73
4-2 Voltage Control Oscillator Circuit 75
4-3 Divider Circuit 77
4-4 Phase Detector and Charge Pump Circuit 86
4-5 Conclusion 87

Chapter 5 Electromagnetic Interference solution 90
5-1 Introduction 90
5-2 Circuit Analysis 92
5-3 Simulation Results 95
5-4 Experimental Results 100
5-5 Conclusion 105

Chapter 6 Conclusion 107
CHAPTER 1
1. IEEE, “Standard 802.11a,” 1999.
2. J.C. Rudell, O. Jia-Jiunn, R.S. Narayanaswami, G. Chien, J.A. Weldon, L. Li, K.C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson, D. Gerna, M. Otsuka, and P.R. Gray, “Recent developments in high integration multi-standard CMOS Transceivers for personal communication systems,” IEEE, International symposium for low power electronics and device, pp. 149-154, 1998.
3. C.D. Hull, R.R. Chu, and J.L. Tham, “A direct-conversion receiver for 900MHz (ISM Band) spread spectrum digital cordless telephone,” Digest of technical papers, International Solid-State Circuits Conference, pp. 344-345, 1996.
4. K. Feher, “Digital Communications,” Englewood Cliffs, NJ: Prentice Hall, 1995.
5. R. Steele, “Mobile Communications,” Piscataway, NJ: IEEE press, 1992.


CHAPTER 2
1 W.R. Liou, C.A. Tsai, A.Y. Wu, and M.L. Yeh, “A 2.4-GHz CMOS RF Receiver Front End,” The 2002 VLSI Design/CAD Symposium, Taitung, Taiwan, pp. 51-54, 2002.
2 D.K. Shaeffer, and T.H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, Vol. 32, pp. 745-759, 1997.
3 H. Kim, X. Li, and M. Ismail, “A 2.4-GHz CMOS Low Noise Amplifier using an Inter-stage Matching Inductor,” Circuits and Systems, 2000. 42nd Midwest Symposium on, Vol. 2, pp.185-188, 2000.
4 X. Li, H.S. Kim, M. Ismail, and H. Olsson, “A Novel Design Approach for GHz CMOS Low Noise Amplifiers,” IEEE J. of Solid-state Circuits, Vol.2, pp.285-288, 1999.
5 A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and mixer,” ISSCC Dig. Tech. Papers, Vol.39, pp. 50-51, 1996.
6 G. Hayashi, H. Kimura, H. Simomura, and A. Matsuzawa, “A 9-mW 900-MHz CMOS LNA with mesh arrayed MOSFETs,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 84-85, 1998.
7 C.S. Kim, C.H. Kim, Y.C. Hyeon, H.K. Yu, K. Lee, and K.S. Nam, “A fully integrated 1.9-GHz CMOS Low Noise Amplifier,” IEEE Microwave and Guided Wave Letters, Vol. 8, No. 8, pp. 293-295, 1998.
8 S. Yang, R. Mason, and C. Plett, “CMOS LNA in wireless applications,” 1999 IEEE 49th Vehicular Technology Conference, Vol. 3, pp. 1920-1924, 1999.


CHAPTER 3
1. W.R. Liou, C.A. Tsai, M.L. Yeh and A. Y. Wu, “A Low-Voltage CMOS 4.4-GHz LC Voltage Control Oscillator Design,” Japanese Journal of Applied Physics, Vol. 42, pp.6400-6404, 2003.
2. W.R. Liou, C.A. Tsai, A.Y. Wu, and M.L. Yeh, “A 2.4GHz CMOS RF Transmitter,” The 2003 VLSI Design/CAD Symposium, Hualien, Taiwan, B4-8, 2003.
3. B. Razavi, “RF Transmitter Architectures and Circuits,” IEEE Custom Integrated Circuits Conference, pp. 197-204, 1999.
4. C.Y. Wu, and H.S. Kao, “A 2-V Low Power CMOS Direct-conversion Quadrature Modulator with Integrated Quadrature Voltage-Controlled Oscillator and RF Amplifier for GHz RF Transmitter Applications,” IEEE conference for Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, pp. 123-134, 2002.
5. K. C. Tsai, and P. R. Gray, “A 1.9-GHz, 1-W CMOS Class E Power Amplifier for Wireless Communications,” IEEE J. Solid-State Circuits. Vol. 34, pp.962-970, 1999.
6. Y.J.E. Chen, M. Hamai, D. Heo, A. Sutono, S. Yoo, and J. Laskar, “RF Power Amplifier Integration in CMOS Technology,” IEEE MTT-S Digest, Vol. 1, pp. 545-548, 2000.
7. S.J. Yoo, H.J. Ahn, M.M. Hella, and M. Ismail, “The Design of 433-MHz Class AB CMOS Power Amplifier,” IEEE Mixed-Signal Design conference, pp. 36-40, 2000.
8. D. Gerna, A. Giry, D. Manstretta, D. Bolot, and D. Pache, “1-W 900-MHz Direct Conversion CMOS Transmitter for Paging Applications,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 191-194, 2001.
9. C. Lam, and B. Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-μm CMOS Technology,” IEEE J. Solid-State Circuits. Vol. 35, pp. 788-794, 2000.
10. T.H. Lee, “The design of CMOS Radio Frequency Integrated Circuits,” Cambridge University Press, New York 1998.
11. Y.K. Moon and K.S. Yoon, “A 3.3 V CMOS PLL with a two-stage self-feedback ring oscillator,” TENCON 99. Proceedings of the IEEE Region 10 Conference, Vol. 1, pp. 286-289, 1999.
12. A. Dec and K. Suyama, “A 1.9-GHz CMOS VCO with micro machined electromechanically tunable capacitors,” IEEE J. Solid-State Circuits. Vol. 358, pp.1231-1237, 2000.
13. M. Zannoth, B. Kolb, J. Fenk and R. Weigel, “A full integrated VCO at 2 GHz,” IEEE ISSCC Dig. Tech, pp.224-227, 1998.
14. D. Ham and A. Hajimiri, “Design and optimization of a low noise 2.4 GHz CMOS VCO with integrated LC tank and MOSCAP tuning,” IEEE Int. Symp. Circuits and Systems, Vol. 1, pp. 331-34, 2000.
15. A. Ali and L. Tham, “A 900 MHz frequency synthesizer with integrated LC voltage control oscillator,” IEEE ISSCC Dig. Tech, pp. 372-375, 1996.
16. IEEE, “International Standard 802.11a. IEEE Standard,” 2000.
17. T. S. Aytur and B. Razavi, “A 2 GHz, 6-mW BiCMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, Vol. 30, pp. 14571462, 1995.
18. C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz CMOS Voltage-Controlled Oscillator,” IEEE International Solid-State Circuits Conference, pp. 117-120, 1999.

CHAPTER 4
1. J. Craninckx, and M.S.J. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, Vol. 32, pp. 736-744, 1997.
2. N. Troedsson and H. Sjoland, “High performance 1-V 2.4-GHz CMOS VCO,” IEEE Asia-Pacific Conference, pp. 185-188, 2002.
3. H.R. Rategh and T.H. Lee, “Multi-GHz Frequency Synthesis & Division,” Kluwer Academic Publishers, 2001.
4. J. Craninckx, and M.S.J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS,” IEEE J. Solid-State Circuits, Vol. 31, pp. 890-897, 1996.
5. H.R. Rategh, H. Samavati and T.H. Lee, “A 5-GHz, 32-mW CMOS frequency synthesizer with an injection locked frequency divider,” IEEE VLSI Circuits Conference, pp. 113-116, 1999.
6. J.A. Hong and M. Ismail, “GHz programmable dual-modulus prescaler for multi-standard wireless applications,” IEEE International Symposium, Vol. 1, pp. I137-I140, 2002.
7. W.H. Lee, J.D. Cho, and S.D. Lee, “A high speed and low power phase frequency detector and charge pump,” IEEE Design Automation Conference, Vol. 1, pp. 269-272, 1999.

CHAPTER 5
1. W.R. Liou, C.A. Tsai, M.L. Yeh, and A.Y. Wu, “A Novel Current control pad for Electromagnetic Interference solution,” Japanese Journal of Applied Physics, Vol. 43, pp. 2462-2426, 2004.
2. F. Fiori and S. Pignari, “Assessment of digital integrated circuit electromagnetic emission based on radiated power evaluation,” IEEE conference, Vol. EMC-43, pp. 531-537, 2001.
3. N. Speciale, and G. Masetti, “On the Effects of Electromagnetic Interferences Conducted on the Power Supply Rails of Integrated JFET/Bipolar Operational Amplifiers,” XIV Design of Circuit and Systems Conference (DCIS`99), pp. 779 -782, 1999.
4. H.P. Yee, “An EMI suppression MOSFET driver,” IEEE Conference. Vol. 1, pp. 242-248, 1997.
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