(18.232.50.137) 您好!臺灣時間:2021/05/06 17:29
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳立偉
研究生(外文):Li-Wei Chen
論文名稱:以實際RLCTable為基礎的低功率匯流排編碼系統
論文名稱(外文):Dynamic Bus Encoding based on Realistic RLC Table with Low Power Coonsideration
指導教授:賴飛羆賴飛羆引用關係
指導教授(外文):Fei-Pei Lai
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:34
中文關鍵詞:動態
外文關鍵詞:BusLow PowerDynamicRLC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:72
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
In the years to come, interconnect will be a challenge to surmount for deep sub-micron (DSM) technologies. The use of DSM technology increases the capacitive and inductive coupling which leads to severe crosstalk noise, more power dissipation and malfunction of the chip between neighboring wires. We propose a method to reduce crosstalk noise on buses based on dynamic coding scheme. The proposed method deals with capacitive and inductive effects at the same time by using the realistic RLC table and the segmented bus-invert method. The experimental results show that our approach reduces bus power consumption up to 7%.
ABSTRACT 5
CHAPTER 1 INTRODUCTION 6
CHAPTER 2 BACKGROUND 8
2.1 CAPACITIVE EFFECTS 8
2.1.1 Self Capacitance 8
2.1.2 Coupling Capacitance 11
2.2 INDUCTIVE EFFECTS 13
2.2.1 Self Inductance 13
2.2.2 Partial Self Inductance 14
2.2.3 Mutual Inductance 14
2.3 THE RLC CIRCUIT FOR ON-CHIP BUS ARCHITECTURE 16
CHAPTER 3 DYNAMIC BUS ENCODING SCHEME 18
3.1 MOTIVATION 18
3.2 DBE_RLCT ARCHITECTURE 19
3.3 REDUCE CROSSTALK EFFECT BY RLC TABLE 20
3.4 RLC TABLE 23
3.4.1 Architecture 23
3.4.2 Generation of RLC table 23
3.4.3 Compression of RLC table 24
CHAPTER 4:EXPERIMENTAL SETUP AND RESULT 27
4.1 EXPERIMENTAL ENVIRONMENT 27
4.2 EXPERIMENTAL RESULT 27
CHAPTER 5:CONCLUSION 30
BIBLIOGRAPHY 31
[1] G. Moore, Progress in Digital Integrated Electronics, IEDM, 1975.
[2] International Technology Roadmap For Semiconductors, 2001 Edition ; Interconnect, http://public.itrs.net/Files/2001ITRS/Home.htm.
[3] H. Bakoglu, Circuits, interconnections, and packaging for VLSI, Addison-Wesley Pub. Co. Reading, Mass. 1990.
[4] A. Deutsch, et al, ”High-Speed Signal Propagation on Lousy Transmission Lines,” IBM J. Res. Develop., vol. 34, pp. 601-615, 1990
[5] C. Cheng, J. Lilis, S. Lin N.Chang, Interconnect Analysis and Synthesis, Wiley Inter-Science 2000.
[6] T. Sakurai, “Design Challenges for 0.1 m and Beyond”, Asia and South Pacific Design Automation Conference 2000, pp. 553-558.
[7] J. Rabaey, Digital Integrated circuits, Prentice Hall 1996.
[8] S. Hall, G. Hall, J. McCall, High-Speed Digital System Design, Willey Inter-science Publication, John Willey and Sons, 2000.
[9] S. Borkar, “Low power design challenges for the decade”, Asia and South Pacific Design Automation Conference 2001, pp. 293-296.
[10] S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, “A coding framework for low-power address and data busses,” IEEE Trans. On VLSI Systems, v.7 n.2, p. 212-221, June 1999.
[11] L. Benini, G. D. Micheli, E. Macii, M. Poncino, and S. Quer, “Power optimization of core-based systems by address bus encoding,” IEEE Trans. on VLSI System, 6:551-562, Volume: 6, Issue: 4, Dec. 1998, Pages: 554 - 562.


[12] M. Madhu, V. S. Murty, and V. Kamakoti, “Dynamic coding technique for low-power data bus, In IEEE ISVLSI’03, pages 252-253, Feb 2003.
[13] Y. Shin, S. Chas, and K. Choi, “Partial bus-invert coding for power optimization of application-specific systems,” IEEE Trans. on VLSI System, Volume: 9, Issue: 2, April 2001 Pages: 377 - 383.
[14] E. Musoll, T. Kang, and J. Cortadella, “Working-zone encoding for reducing the energy in microprocessor address buses,” IEEE Trans. on VLSI System, 6:568-572, Volume: 6, Issue: 4, Dec. 1998 Pages: 568 – 572.
[15] H. Zhou and D. Wong, “Global routing with crosstalk constraints,” In in Proceedings of DAC-1998, June 1998, Pages: 374 – 377.
[16] I. H-R. Jiang, Y.-W. Chang, and J. Y. Jou, “Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing,” IEEE Trans. on CAD of Integrated Circuits and Systems, 19:999-1010, Volume: 19 , Issue: 9 , Sept. 2000
Pages:999 - 1010.
[17] E. Naroska, S. J. Ruan, F. Lai, U. Schwiegelshohn, and L. C. Liu, “On optimizing power and crosstalk for bus coupling capacitance using genetic algorithm” In in Proceedings of ISCAS03, Volume: 5 , 25-28 May 2003
Pages:V-277 - V-280 vol.5.
[18] A. Deutsch, G. Kopcsay, P. Coteus, C. Surovic, B. Rubin, R. Dunne, T. Gallo, K. Jenkins, L. Terman, R. Dennard, G. Sai-Halasz, B. Krauter, and D. Knebel, “When are trans mission-line effects important for on-chip interconnections?” IEEE Trans. on Microwave Theory Tech, 45:1836-3846, Volume: 45, Issue: 10, Oct. 1997, Pages: 1836 - 1846.
[19] K. Lepak, I. Luwandi, and L.He, “Simultaneous shield insertion and net ordering under explicit rlc noise constraint,” In in Porc. Design Automation Conference, 2001, pages 199-202, 2001.
[20] D. Bailey and B. Benschneider, “Clocking design and analysis for 600-mhz alpha microprocessor,” IEEE J. Solid-State Circuit, Volume: 33, Issue: 11, Nov. 1998, Pages: 1627 - 1633.
[21] L. Vakanas, S. Hasan, A. Cangellaris, and J. L. Prince, “Effects of floating planes in three-dimensional packaging structures on simultaneous switching noise,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, 21:434-440, Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on [see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions on], Volume: 21, Issue: 4, Nov. 1998, Pages: 434 - 440.
[22] J. Silberman, et al, “A 1.0GHz Single-Issue 64b PowerPC Integer Processor,” in Proc. ISSCC-98, San Francisco, Feb. 5-7, 1998, pp. 230-231.
[23] E. E. Davidson, B. D. McCredie, and W. V. Vilkelis, “Long Lossy Lines( ) and Their Impact Upon Chip Performance,” IEEE Trans. Comp. Packaging, Manuf. Technol.-Part B, Vol. 20, No .4, pp.361-375, Nov. 1997.
[24] C. K Cheng, J. Lillis, S. Lin, and N. Chang, “Interconnect Analysis and Synthesis,” John Wiley & Sons, Inc., 1999.
[25] J. Torres, “Advanced Copper Interconnections for Silicon COMS Technologies,” Applied Surface Science, Vol. 91, pp.112-123, Oct. 1995.
[26] A. Deutsch, et all, ”When are Transmission-Line Effects Important for On-Chip Wiring,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997.
[27] A. Deutsch, et all, “The Importance of Inductance and Inductive Coupling for On-Chip Wiring,” Proc. IEEE 6-th Electrical Performance of Electronic Packaging, pp. 53-56, Oct. 1997.
[28] Rung-Bin Lin; Chi-Ming Tsai, “Theoretical analysis of bus-invert coding” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume: 10, Issue: 6, Dec. 2002, Pages: 929 – 934.
[29] M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power i/o, “IEEE Trans. On VLSI System, 3:49-58, Volume: 3, Issue: 1, March 1995, Pages: 49 - 58.
[30] M. Kamon, and et al, “Fasthenry: a multiple-acceler-ated 3-d inductance extraction program,” IEEE Trans on MTT, Volume: 42, Issue: 9, Sept. 1994, Pages: 1750 – 1758.
[31] K. Nabors and J. White, “Fastcap: a multiple-acceler-ated 3-d capacitance extraction program,” IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, Volume: 10, Issue: 11, Nov. 1991, Pages: 1447 - 1459.
[32] Frederick W. Grover, Inductance Calculations Working Formulas and Tables, Dover Publications, 1946.
[33] Dr. Eric Bogatin, What Really Is Inductance?, Bogatin Enterprises Oct 30, 1999.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔