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研究生:黃俊銘
研究生(外文):Chun-Ming Huang
論文名稱:寄生運算最小化的低功率暫存器配置方法
論文名稱(外文):A Novel Methodology to Minimize Spurious Operations for Low Power Register Allocation
指導教授:顧孟愷
指導教授(外文):Mong Kai Ku
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:39
中文關鍵詞:兼容圖寄生運算高階合成最大成本流量變數配置
外文關鍵詞:variable assignmentCDFGHigh-Level SynthesisMax-cost flowNSO
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當運算器的輸入值改變就會造成它的一次開關行為而消耗動態功率。如果這種開關行為發生在運算器的空閒狀態我們稱它為〝寄生運算〞,會消耗不必要的功率。由此可知,輸入變數的配置會決定這種寄生運算是否會在運算器上發生。過去的研究曾提出一個在高階合成使用的變數配置技術,這種技術提出抑制寄生運算且不會增加暫存器或多餘電路的方法。在這篇論文中,我們提出新的方法及有效率的演算法可以解決變數配置的問題且得到最佳化的結果。我們將變數配置的問題轉換一個適當定義的兼容圖中的最小成本完全圖覆蓋問題,然後利用最大成本流量演算法解題,而其中,成本方程式是用寄生運算的數量來定義,我們提供一個有系統的方法計算寄生運算的數量。實驗結果驗證了,這種方法在高階合成的變數配置階段,確實可以找到寄生運算最小化的配置方法,進而減少功率的消耗。
A functional unit consumes dynamic power when a switching activity occurs which means the input values in the registers have changed. We call the occurrence of a switching activity to be spurious when the functional unit is in “idle”. Thereby the assignment method of input variables determines whether or not spurious operations get executed by functional units. Previous researches have presented a variable assignment technique which, when used in high-level synthesis, suppresses spurious operations without adding latches or any other circuitry in front of functional units or registers. In this thesis, we propose the novel methodology and efficient algorithms to solve the variable assignment problem optimally. We apply a graph-theoretical solution of formulating the register assignment problem as a minimum cost clique covering of an appropriately defined compatibility graph and solve it with a max-cost flow algorithm, where the cost function is defined by using the number of spurious operations. Experimental results confirm the viability and usefulness of the approach in minimizing spurious operations during the register assignment phase of the behavioral synthesis process.
Chapter 1 Introduction 1
1.1 Low Power Requirement 1
1.2 Power Dissipation 2
1.2.1 Sources of Power Dissipation 2
1.2.2 Dynamic Power Dissipation 2
1.3 Related Work 4
1.4 Organization 5

Chapter 2 Low Power Design in High Level Synthesis 6
2.1 Introduction to High Level Synthesis 6
2.1.1 Levels of Abstraction 6
2.1.2 High-level Synthesis Algorithms 8
2.2 Control and Data Flow Graph 14
2.2.1 A Language of Representation 14
2.2.2 VDT and CDFG tool 16

Chapter 3 Low Power Register Allocation 19
3.1 Spurious Operations in a Functional Unit 20
3.2 Register Sharing 21
3.3 Variable Assignment Algorithm 24
3.3.1 Max-cost flow formulation 24
3.3.2 The Cost Function 27
3.3.3 The algorithm 29

Chapter 4 Experimental Results 32
4.1 Experiment Flow and Environment 32
4.2 The Experimental Results of Benchmarks 33
4.3 Discussion 36

Chapter 5 Conclusions 37

Bibliography 38
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