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研究生:劉宗德
研究生(外文):Tsung-Te Liu
論文名稱:超寬頻收發機互補式金氧半類比前端設計與實作
論文名稱(外文):Design and Implementation of CMOS Analog Front End for Ultra Wideband Transceiver
指導教授:汪重光汪重光引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:80
中文關鍵詞:超寬頻系統類比前端延遲鎖定迴路時脈產生器接收機低雜訊放大器
外文關鍵詞:Ultra Wideband (UWB)transceiverdelay-locked loop (DLL)clock generatorlow noise amplifier (LNA)analog front end
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由於人們對高速無線通訊的需求,加速推動對於新一代無線通訊系統的開發,而超寬頻系統即為目前新興的無線通訊技術之一。在低成本、低必v消耗以及高系統整合的優勢之下,使用CMOS製程來實現超寬頻接收機為最佳的選擇。本論文探討使用CMOS製程設計與實現兩個位於超寬頻接收機類比前端最重要的電路,分別為低雜訊放大器與時脈產生器電路。
本論文首先會討論低雜訊放大器與時脈產生器電路一般所採用的電路架構以及其設計考量,再進一步提出針對超寬頻系統,使用CMOS製程實現超大型積體電路的硬體電路架構。在低雜訊放大器部分,本論文提出一個不需要任何被動調頻元件,適用於低頻帶超寬頻系統的低必v寬頻CMOS低雜訊放大器。藉著採用共閘級並回授的架構,本低雜訊放大器可以在低必v消耗的情況下達到寬頻的輸入組抗匹配。另外,由於使用電流再利用的技巧,所提出的低雜訊放大器架構可在不消耗多餘必v的情況下輸出更大的增益,並同時減少低雜訊放大器電路對於製程變異的敏感度。在時脈產生器方面,本論文先提出一個具有大操作範圍及適應頻寬特性的延遲鎖定迴路,來實現適用於低頻帶超寬頻系統的低時脈擾動時脈產生器。此延遲鎖定迴路使用數位校正迴路來解決一般常見於大操作範圍延遲鎖定迴路的錯誤鎖定問題,並可進一步加速延遲鎖定迴路的收斂時間。另外,由於使用自我偏壓的技巧,所提出的延遲鎖定迴路架構同時可以適應性的調整頻寬,在大操作範圍及製程、電壓及溫度環境的變異下展現最佳的時脈擾動特性。接下來,本論文提出一個以延遲鎖定迴路為架構,具有低必v消耗、低時脈擾動及大操作範圍特性,適用於超寬頻系統的時脈產生器。利用所提出的數位類比雙迴路適應頻寬延遲鎖定迴路架構,結合互補式的相位偵測性電路,可以確保時脈產生器能在大操作範圍下輸出低時脈擾動的時脈。另外,由於使用自我回授的技巧,可以讓位準轉換器電路降低至少50%的必v消耗。最後,本論文呈現低雜訊放大器與時脈產生器電路晶片的量測結果,藉以驗證所提出電路架構的弁鄐峈穛{。
The desire for high-speed wireless data communication drives the exploration of the emerging wireless technology, Ultra Wideband (UWB). The CMOS technology is the most promising technology for efficient VLSI implementation of a UWB transceiver because of its low cost, low power consumption, and high system level integration. This thesis presents the CMOS design and implementation of the low noise amplifier (LNA) and clock generator circuits, the most critical parts of the analog front end in a UWB transceiver.
The general architectures and design issues of the LNA and clock generator circuits will be discussed followed by the CMOS VLSI implementations for UWB system. A low-power wideband CMOS LNA without requiring any passive tuning component for low-band UWB application is first described. The wideband input impedance matching is ensured by employing the common-gate shunt-shunt feedback topology with low power consumption. The current-reuse technique applied in the proposed LNA architecture not only provides additional gain but also reduces the process technology sensitivity of the LNA. Then, a low-jitter clock generator for low-band UWB application based on a wide-range adaptive-bandwidth delay-locked loop (DLL) is presented. The false-locking problem commonly along with the wide-range DLL is eliminated by the digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristics over a wide frequency range and across process, voltage, and temperature (PVT) variations. A DLL based low-power low-jitter wide-range clock generator for UWB application is also described. The proposed analog-digital dual-loop adaptive-bandwidth structure in conjunction with a complementary phase detector ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. Finally, the experimental data for the LNA and the clock generator prototypes are presented to demonstrate the functionalities and performances of the proposed circuit architectures.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Thesis Overview . . . . . . . . . . . . . . . . .2
2. Ultra Wideband Communication System Introduction . . . . . . . . . . . . . . . 5
2.1 UWB System Overview . . . . . . . . . . . .5
2.1.1 The Characteristics of UWB Impulse Radio . . . . 6
2.1.2 Spectrum Allocations of UWB System . . . . . . ..8
2.2 Low-Band UWB Transceiver Architectures . . . . . .9
2.2.1 Most-Digital UWB Transceiver . . . . . . . . . . .9
2.2.2 Analog Correlator Based UWB Transceiver . . . 10
2.2.3 Performance Analysis . . . . . . . . . . . . . 11
3. CMOS Low Noise Amplifier Design for Low-Band Ultra Wideband System . . . . . . . . . . . . .. . . . . .15
3.1 LNA Design and Analysis . . . . . . . . . . . . .15
3.1.1 Impedance Matching . . . . . . . . . . . . . . . .16
3.1.2 Noise Modeling and Analysis . . . . . . . . . . 17
3.1.3 LNA Architectures . . . . . . . . . . . . . . . 20
3.2 Implementation of a Wideband CMOS LNA for Low-Band Ultra Wideband System . . . . . . . . . . . .23
3.2.1 A Low-Power Wideband CMOS LNA Design . . . . . 23
4. CMOS Clock Generator Design for Ultra Wideband System . . . . . . . . . . 31
4.1 Clock Generator Architectures . . . . . . . . 31
4.1.1 PLL Based Clock Generator Architecture . . 32
4.1.2 DLL Based Clock Generator Architecture . . . 33
4.2 DLL Based Clock Generator Design and Analysis . .34
4.2.1 Loop Design . . . . . . . . . . . . . . . . 35
4.2.2 Jitter Analysis . . . . . . . . . . . . . . . 40
4.2.3 Operating Range Analysis. . . . . . . 44
4.3 Implementation of CMOS DLL Based Clock Generators for Ultra Wideband System . . . . . . . . . . 45
4.3.1 A Self-Correcting Adaptive-Bandwidth CMOS DLL Based Clock Generator Design . . . . . . .46
4.3.2 A Dual-Loop Adaptive-Bandwidth CMOS DLL Based Clock Generator Design . . . . . . 54
5. Experimental Results . . . . . . . . . . . . . . .65
5.1 An Experimental CMOS Wideband LNA . . . . . . 65
5.1.1 Low-Power CMOS Wideband LNA Experimental Results .65
5.2 Experimental CMOS DLL Based Clock Generators . . 68
5.2.1 Self-Correcting Adaptive-Bandwidth CMOS DLL Based Clock Generator Experimental Results . . . . . . . . . . 68
5.2.2 Dual-Loop Adaptive-Bandwidth CMOS DLL Based Clock Generator Experimental Results . . . . .70
6. Conclusion . . . . . . . . . . . . . . . . . . . . . 75
Bibliography . . . . . . . . . . . . . . . . . . . . . . 77
[1] Http://bwrc.eecs.berkeley.edu/Research/UWB/pubs.htm
[2] “First report and order in the matter of revision of Part 15 of the commission’s rules regarding Ultra-Wideband transmission systems,” FCC, released, ET Docket 98-153, FCC 02-48, Apr. 22, 2002.
[3] I. G. Proakis, Digital Communications, Fourth Ed., Boston: McGraw-Hill, 2001.
[4] I. O. Donnell, S. W. Chen, B. T Wang, and R. Broderson, “An integrated low power ultra-wideband transceiver architecture for low rate indoor wireless systems,” IEEE CAS Workshop on Wireless Communications and Networking, Sep. 2002.
[5] D. Kelly, S. Reinhardt, R. Stanley, and M. Einhorn, “PulsOn second generation timing chip: Enabling UWB through precise timing,” IEEE Conference on Ultra Wideband Systems and Technologies Dig. Papers, pp. 117-121, May 2002.
[6] B. Razavi, RF Microelectronics, New Jersey: Prentice-Hall, 1998.
[7] A. A. Abidi, “High-frequency noise measurements on FETs with small dimensions,” IEEE Tran. Electron Devices, vol. 33, pp. 1801-1805, Nov. 2000.
[8] B. Razavi, R.-H. Yan, and K. F. Lee, “Impact of distributed gate resistance on performance of MOS devices,” IEEE Trans. Circuits Syst. I, vol. 41, pp. 750-754, Nov. 1994.
[9] Albert van der Ziel, Noise in Solid State Devices and Circuits, New York: Wiley, 1986.
[10] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cambridge University Press, 1998.
[11] A. Belilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6GHz wireless receivers,” ISSCC Dig. Tech. Papers, pp. 382-383, Feb. 2004.
[12] A. Ismail and A. Abidi, “A 3 to 10GHz LNA using a wideband LC-ladder matching network,” ISSCC Dig. Tech. Papers, pp. 384-385, Feb. 2004.
[13] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Noise canceling in wideband CMOS LNAs,” ISSCC Dig. Tech. Papers, pp. 406-407, Feb. 2002.
[14] A. R. Shahani, D. K. Shaeffer, and T. H. Lee, “A 12 mW wide dynamic range CMOS front-end for portable GPS receivers,” ISSCC Dig. Tech. Papers, pp. 368-369, Feb. 1997.
[15] B. Kim, T. Weigandt, and P. Gray, “PLL/DLL system noise analysis for low jitter clock synthesizer design,” in Proc. Int. Symp. Circuits and Systems, vol. 4, pp. 31-38, June 1994.
[16] M.-J. E. Lee et al.,“Jitter transfer characteristics of delay-locked loops - theories and design techniques,” IEEE J. Solid-State Circuits, vol. 38, pp. 614-621, Apr. 2003.
[17] J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[18] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive bandwidth DLLs and PLLs using regulating supply CMOS buffers,” in IEEE Sym. VLSI Circuits Dig. Tech. Papers, pp. 124-127, June 2000.
[19] J. Kim, M. A. Horowitz, and G.-Y. Wei, “Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 860-869, Nov. 2003.
[20] R. van de Beek, E. Klumperink, C. Vaucher, and B. Nauta, “Low-jitter clock multiplication: a comparison between PLLs and DLLs,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 555-566, Aug. 2002.
[21] S. Kuboki, K. Kato, N. Miyakawa, and K. Matsubra, “Nonlinearity analysis of resistor string A/D converters,” IEEE Trans. Circuits Syst. II, vol. CAS-29, pp. 383-390, June. 1982.
[22] Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M.-K. Kim, “An all-analog multiphase delay-lock loop using a replica delay line for wide-range operation and low-jitter performance,” IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
[23] D. J. Foley and M. P. Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator,” IEEE J. Solid-State Circuits, vol. 36, pp. 417-423, Mar. 2001.
[24] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, June 2000.
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1. 賈馥茗 (1968)〈自知與大學生活之調適〉,《師大學報》,第13期,頁102-104。
2. 藍三印 (1995)〈如何建立良好的人際關係〉,《學生輔導雙月刊》,第36期,頁25。
3. 簡茂發 (1978)〈父母教養態度與兒童生活適應之關係〉,《師範大學教育心理學報》,第11期,頁1-65。
4. 黃葳威 (1993)〈新傳播科技與人際傳播:一個跨文化的觀察〉,《輔仁大學傳播文化》,創刊號,頁190-196。
5. 黃堅厚 (1979)〈國小及國中生內外控信念之研究〉,《師範大學教育心理學報》,第12期,頁1-52。
6. 黃世雄 (1994)〈台灣地區外籍勞工生活適應問題及相關因素之研究〉,中國文化大學勞工研究所碩士論文,頁14-158。
7. 許錫珍,蘇建文、邱連煌 (1979)〈兒童制握信念與父母制握信念以及社經水準的關係〉,《測驗年刊》,第26輯,頁37-46。
8. 孫敏華 (1998)〈軍中自我傷害之研究─基層連營輔導長意見調查〉,《復興崗學報》,第六十八期,頁144。
9. 洪光遠 (1998)〈新新人類部隊生活適應問題的探討〉,《軍事社會科學半年刊》,創刊號,頁131-144。
10. 洪光遠 (1997)〈規劃式管理對軍事院校新生適應之影響〉,《復興崗學報》,第六十一期,頁196。
11. 卓淑玲、邱發忠 (1999)〈士兵生活適應問題、因應策略及相關變項關係之初探〉,《復興崗學報》,第六十八期,頁166-198。
12. 江中信 (1995)〈人際傳播之定義、功能及理論基礎〉,《海軍軍官學校學報》,第五期,頁105-110。
13. 朱美珍 (1998b)〈現代青年軍旅生涯適應問題的探討〉,《軍事社會科學半年刊》,創刊號,頁156-175。
14. 朱美珍 (1998a)〈軍校學生人際關係與生活適應之研究─以政戰學校為例〉,台北:復興崗學報,第六十三期,頁162。
 
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