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研究生:張龍豪
研究生(外文):Lung-Hao Chang
論文名稱(外文):A Prototype Silicon IP Design and Implementation for On-chip Transmission
指導教授:吳安宇吳安宇引用關係
指導教授(外文):An-Yeu Wu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:92
語文別:中文
論文頁數:60
中文關鍵詞:晶片內傳送
外文關鍵詞:on-chip transmission
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近幾年來系統單晶片積體電路都採用共用匯流排的架構來連接所有的元件,然而當製程進步到0.18微米以下,使用匯流排的架構會有大量的繞線面積、嚴重的信號偶合和劇烈的接線延遲等問題,造成設計上的困難。此外,傳統的設計方式是使用整體脈衝信號來控制所有的元件,在未來晶片內要掌握將近上億的電晶體數目,如此會造成同步上的問題。本論文提出另一種晶片內傳送的原型架構來減輕上述問題。
晶片內傳送系統使用串列序列轉換器來減少接線數目,內部使用了兩組環形震盪器來產生所需的串列傳送頻率,透過傳送端產生的控制訊號,同時操作兩端的震盪器來傳送及接收串列資料。有了此基本的架構,可建造出環狀網路的接續器的弁遄A裡面除了有2組串序列傳送接收器來傳收兩端接續器的資料外,還有一個控制電路來執行封包判斷及送收的弁遄C可看出此環狀電路使用兩個不同的脈衝傳遞封包資料,捨棄目前常用的整體同部傳送方式。最後若接續器個數增加,則使用可變動的八角形架構來改善。
本論文採用聯電0.18微米製程來實現4個接續器晶片內傳送的架構,由模擬結果可知內部震盪頻率可達770MHz且消耗了11.7微瓦的必v。
In recent years, there has been a growing interest in using bus architecture to connect all the components in the system-on-chip integrated circuit. However, the use of shared bus in chips poses design challenges in numerous routing wire area, serious signal coupling, and heavy wire delay as technologies migrate below 0.18um. Additionally, conventional design method has global clock signal for operating all the elements so in the future billions of transistors would be handled on the single chip and it may cause problems with synchronization. A prototype of on-chip transmission architecture is proposed and implemented to alleviate these problems
The on-chip transmission uses parallel-serial conversion between modules for reducing wiring area. To synchronize the links in two modules, two independent ring oscillators are used to provide serialized/deserialized clock. The sender has controller to command a pair of oscillators for transmitting and receiving serial data clocked by oscillator frequency. Having this basic robust structure, we build a repeater which has two sets of parallel-serial conversion for bidirectional paths and informs our ring-based on-chip transmission structure. Furthermore, the structure evolves two clock domains, internal and external clocks with easy synchronous method, to transfer our packet data instead of using global synchronization. Finally, the scalable octagon structure can apply to this design when modules are increased.
This structure was implemented in a UMC 0.18um CMOS process with four repeaters. Simulation results show that the oscillator frequency achieves about 770MHz with almost identical margins. The nanosim result about on-chip transmission architecture operates successfully with links running at 770MHz and consumes 11.7uW.
Abstract i
Table of Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview 3
Chapter 2 Overview of on-chip Communication Architecture 5
2.1 System-on-Chip Communication Architectures 5
2.2 On-chip Communication Design Issues 9
2.3 Relative Works 11
Chapter 3 Serial Data Transfer 17
3.1 Ring Oscillator Architecture 17
3.2 Analyzing and Realizing Serial Transfer Design 20
3.3 Summary 23
Chapter 4 Basic Building Blocks for On-chip Transmission 25
4.1 Serializer and Deserializer 26
4.2 Sender and Receiver Circuit 30
4.3 The Repeater Architecture 32
4.4 Summary 34
Chapter 5 Design of a 2 × 2 On-chip Transmission Architecture 37
5.1 Ring Topology 37
5.2 Octagon Routing 41
5.3 Summary 45
Chapter 6 Implementation Results 47
6.1 VLSI Architecture 47
6.2 The 2 × 2 on-chip Transmission Architecture 48
6.3 Summary 53
Chapter 7 Conclusions 55
7.1 Summary 55
7.2 Future Work 56
Bibliography 59
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