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研究生:呂嘉祥
研究生(外文):Chia-Hsiang Lu
論文名稱:5.2-GHz射頻CMOS頻率合成器
論文名稱(外文):An Agile 5.2-GHz RF CMOS Frequency Synthesizer
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:55
中文關鍵詞:鎖相迴路頻率合成器無線區域網路
外文關鍵詞:frequency synthesizerPLLwirelessLAN
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近幾年,無線通訊的長足進步已逐漸取代有線傳輸成為現今最無可取代的通訊模式。急速成長的無線區域網路市場也極力的帶動高傳輸速率與傳輸量的需求。

在本論文裡,我們設計及呈現了一個以無線通訊為取向,操作在5GHz頻帶,以鎖相迴路為架構的頻率合成器。以低雜訊和快速鎖定的想法,我們加入了可適性的電路,以改變頻寬的方式來緩衝突波載波比與鎖定時間,借由一開始加大的頻寬增加鎖定的速度,以及鎖定後,縮小的頻寬來改善相位雜訊。電路上,可變的頻寬是藉著偵測相位頻率偵測器輸出的相位差,經由改變充電泵的電流來實現。震盪器是由可變電容及螺旋電感來完成。除頻器由脈衝吞嚥計數器的架構所組成,採用源極偶合邏輯用以操作在高速的頻率之下。此使用1.8伏電壓,消耗功率20毫瓦,操作在5GHz頻帶的頻率合成器已使用台積電0.18微米互補金氧半導體製程實作完成。
Wireless communication has undergone an incredible development over last few years, and it’s gradually replacing the cable communication to become the most important part of the modern world. The growing wireless LAN market has generated increasing interest in technologies enabling higher data rates and capacity than initially deployed systems.

A 5.2-GHz PLL-based frequency synthesizer for wireless LAN applications is presented in this thesis. This PLL employs an adaptation scheme for low noise and fast settling. Adaptive bandwidth charge-pump relaxes the design tradeoffs between spurs level and settling time. The adaptation consists of tuning the charge-pump current by the phase error between output and reference frequency. The tracking capability is enhanced by extending loop bandwidth and a low phase noise clock signal is generated by a narrow loop bandwidth. The oscillator is implemented by the hallow-coil spiral inductors. The frequency divider adopts pulse-swallow architecture and uses source-coupled logic to reduce the switching noise. Circuit techniques were used to achieve low-power dissipation. The frequency synthesizer has been fabricated in a 0.18-μm CMOS technology and operates at 5.2 GHz while consuming 20 mW from a 1.8-V supply.
Chapter 1 Introduction 1

1.1 Motivation 1
1.2 Design Challenges 2
1.3 Thesis Overview 3

���nChapter 2 The Basics of Frequency Synthesizers 6

2.1 General Considerations 6
2.1.1 Phase Noise 6
2.1.2 Spurs 7
2.1.3 Settling Time 9
2.2 Frequency Synthesizer Fundamentals 9
2.2.1 The Concepts of PLL 9
2.2.2 Phase Frequency Detector (PFD) 10
2.2.3 Charge Pump (CP) 11
2.2.4 Voltage-Controlled Oscillator (VCO) 13
2.2.5 Frequency Divider 14
2.2.6 Loop Filter (LF) 15
2.3 Noise Analysis in PLL 17
2.3.1 Noise at Input 18
2.3.2 Noise of VCO 18
2.4 Closed-Loop PLL Analysis 20
2.4.1 Dynamics of Simple PLL 20
2.4.2 Third-Order PLL 24
2.4.3 Fourth-Order PLL 25
2.5 Summary 26

���nChapter 3 Realization of a CMOS Frequency Synthesizer 27

3.1 Behavioral Simulation 27
3.2 Circuits Implementation 28
3.2.1 Phase-Frequency Detector 28
3.2.2 Adaptive-Bandwidth-Controlled Charge-Pump 30
3.2.3 Voltage-Controlled Oscillator 36
3.2.4 Frequency Divider 38
3.3 Stability Analysis 43
3.4 Frequency Synthesizer 45
3.5 Summary 46

���nChapter 4 Experimental Results 47


���nChapter 5 Conclusion 53


���nBibliography 54
[1] IEEE Std 802.11a/D7.0-1999, “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5GHz Band.”
[2] ETSI, “Broadband Radio Access Networks (BRAN); HIPERLAN type 2 technical specification; Physical (PHY) layer,” Aug. 1999.
[3] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
[4] F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. on Communications, vol. 28, pp. 1849-1858, Nov. 1980.
[5] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[6] B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.
[7] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.

[8] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University, 1998.
[9] T. H. Lee and Ali Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol.35, pp.326-336, Mar. 2000.
[10] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor Application Note, no. 1001, May 1996.
[11] Thomas H. Lee, Hirad Samavati, and Hamid R. Rategh, “5-GHz CMOS Wireless LANs,” IEEE J. Solid-State Circuits, Jan. 2002.
[12] Joonsuk Lee and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, Aug. 2000.
[13] A. R. Kral, “A 2.4GHz Frequency Synthesizer in 0.6mm CMOS,” MS thesis, Dept. of Electrical Engineering, University of California Los Angeles, Mar. 1998.
[14] Christopher Lam and Behzad Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4um CMOS Technology,” IEEE J. Solid-State Circuits, May 2000.
[15] C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S.Wong, “A Physical Model for Planar Spiral Inductors on Silicon,” in Int. Electron Devices Meeting, 1996, pp. 155–158.

[16] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuit, vol. 35, June 2000.
[17] Roland E. Best, Phase-Locked Loops, McGraw-Hill, 1998.
[18] F.M. Gardner, Phaselock Techniques, Second Ed., New York: McGraw-Hill, 1993
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