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研究生:陳昱勛
研究生(外文):Yu-Hsun Chen
論文名稱:輔以數位自行校正之開迴路殘值增益六位元導管式類比數位轉換器
論文名稱(外文):A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:68
中文關鍵詞:數位自行校正導管式類比數位轉換器開迴路殘值增益
外文關鍵詞:open-loop residue amplificationdigital self-calibrationpipelined A/D converter
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隨著積體電路製程持續進步,供給電壓與電晶體體積急速減小,數位電路的運算能力也不斷增加。但對類比電路而言,較低的供給電壓與相對較大的臨界電壓,反而造成了電路設計上的困難。類比數位轉換器連結了類比世界與數位電路。由於在他的使用上延伸了純類比信號與類比數位混和信號的運作,類比數位轉換器往往成為了資料運算應用上的瓶頸,限制了整個系統的速度與精確度。

由於輕便性與系統單晶片整合的需求持續增加,低功率消耗與深次微米製程的相容性均成為當今類比類為轉換器的重要設計考量。在系統單晶片的實現上,資料轉換器往往與威力強大的數位訊號處理系統整合在同一顆單晶片內,造成了整體設計上熱能與功率消耗的限制。

在這篇論文中,我們描述了一個輔以數位自動校正之開迴路殘值增益六位元管線式類比數位轉換器的實現與量測結果。在一位元轉換級的架構設計上,我們採用了開迴路放大器,使整個系統得以在高速運作下有著極低的功率消耗。而使用固定轉換電導的偏壓電路技術,讓開迴路放大器不因製程與溫度的偏移而受到影響。比較器偏移與全幅錯誤則以數位自動校正機制成功的去除。此外,這個設計沒有用到MIM或PIP電容,因此我們能夠在數位製程上實現此電路。本設計使用0.13微米製成與1.2伏特的供給電壓,當類比數位轉換器運作在五億赫茲時脈速率時,僅消耗13.2毫瓦。
By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters provide the link between the analog world and the digital system. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision.

For the increasing demand for portability and system-on-a-chip (SoC) integration, low-power dissipation and the compatibility with deep-submicron technology have emerged as important metrics in state-of-the-art ADC design. In SoC implementations, data converters are embedded on the same chip with powerful fine-line digital signal processing, resulting in a limited budget for their total heat and power consumption.

In this thesis, we describe the implementation and measurement results of a 6-bit pipelined ADC with open-loop residue amplification and digital self-calibration. Employing open-loop amplifiers in one-bit-conversion-per-stage architecture, the circuit operates in high speed and low power consumption. Using a constant-gm biasing technique, the open-loop amplifier is process-and-temperature insensitive. Comparator offset and full-scale error are removed by digital self-calibrated correction mechanism. Because of no requirement of MIM or PIP capacitors, this design is capable to be fabricated in digital process. Designed in a 0.13-μm technology and powered 1.2-V supply voltage, the A/D converter operates at 500-MHz clock-rate while dissipating 13.2 mW.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 Fundamentals of Analog-to-Digital Converter 5
2.1 Introduction 5
2.2 ADC Performance Metrics 5
2.2.1 Signal to Noise Ratio (SNR) 5
2.2.2 Signal to Noise and Distortion Ratio (SNDR) 7
2.2.3 Resolution and Effective Number of Bits (ENOB) 7
2.2.4 Nonlinearity 7
2.3 Architectures of Analog-to-Digital Converters 9
2.3.1 Flash ADC 9
2.3.2 Two Step Flash ADC 10
2.3.3 Pipelined ADC 10
2.3.4 Cyclic ADC 11
2.4 Summary 12

Chapter 3 The Design of Pipelined A/D Converter 13
3.1 Introduction 13
3.2 Key Building Blocks of Pipelined ADC 13
3.3 Conventional Conversion Stage Design 16
3.3.1 Switched Capacitor Technique 17
3.3.2 Switched Capacitor MDAC 18
3.4 Low-Power-High-Speed Conversion Stage Design 19
3.4.1 Common Source Operation 19
3.4.2 Open-Loop Residue Amplifier 25
3.4.3 Constant-Gm Biasing 28
3.4.4 Open-Loop Residue Amplifier with Constant-Gm Biasing 29
3.4.5 Dynamic Comparator 30
3.5 Nonideality considerations 31
3.5.1 Nonlinearity 31
3.5.2 Offset Error 33
3.5.3 Full-Scale Error 34
3.5.4 Digital Self-Calibration Algorithm 35
3.6 Behavioral Model of Pipelined ADC 37
3.6.1 Mathematical Modeling 37
3.6.2 Parameter Estimation 39
3.7 Summary 40

Chapter 4 Circuit Implementation 41
4.1 Introduction 41
4.2 Sample-and-Hold Circuit 42
4.3 Constant-Gm Biasing Circuit 44
4.4 Open-Loop Amplifier 45
4.5 Dynamic Comparator 47
4.6 Reference Circuit 48
4.7 Clock Generator and Divider 49
4.8 Digital Circuit and Output Buffer 50
4.9 The Simulation Results of Pipelined ADC 51
4.10 Layout and Floorplan 53
4.11 Summary 54

Chapter 5 Test and Experimental Results 57
5.1 Introduction 57
5.2 Test Setup 57
5.2.1 Test Equipments 57
5.2.2 Print Circuit Board Design 58
5.4 Experimental Results 60
5.5 Summary 63

Chapter 6 Conclusions 65
6.1 Conclusions 65
6.2 Future Works 65

Bibliography 67
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