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研究生:劉源雙
研究生(外文):Yuan-Shuang Liu
論文名稱:使用可程式邏輯閘陣列實現時脈抖動之量測智產權
論文名稱(外文):The FPGA implementation of a jitter measurement infrastructure IP
指導教授:黃俊郎黃俊郎引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:92
語文別:英文
論文頁數:66
中文關鍵詞:智產權可程式邏輯閘陣列時脈抖動
外文關鍵詞:FPGAIPclock jitter
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近幾年來,信號抖動的課題,日益重要並被熱切的討論與研究。隨著積體電路技術上的持續進步,網路、匯流排與高速數位系統的操作速度亦不斷地提昇。對於現今高速網路設備元件而言,信號抖動(Jitter)已成為設計人員所相當重視的一種信號特性,而在測試上亦是一項挑戰。
現階段而言;高速信號抖動之量測,仍需仰賴昂貴之自動測試設備,這也意味著需要較長的測試時間。甚至,面臨電子電路高度整合的趨勢,信號抖動的量測亦日亦困難。

因此本篇論文介紹信號抖動相關的定義與量測方法,並提出使用可程式邏輯閘陣列(FPGA)實現時脈抖動之量測智產權(Infrastructure IP,IIP);將低成本的信號抖動量測的內建自我量測電路(BIST) [6],實現在可程式邏輯閘陣列中。目標是提供一個低成本和可重複使用的時脈抖動量測的智產權,可以很方便和有效率地被應用在可程式邏輯閘陣列中;也就是需要量測時脈抖動時,將時脈抖動之量測智產權載入可程式邏輯閘陣列中,進行量測;量測完成時,再將此量測智產權移除。如此一來可以達到非常彈性應用的目的,亦不會佔用可程式邏輯閘陣列的空間。

最後,使用任意信號產生器產生含抖動成份之時派信號 100Mhz,最大均方根抖動信號達 668.5 ps,再進一步利用此時脈信號來驗證此抖動量測智產權之量測;量測結果若誤差小於+-10%,其最佳量測之範圍為 250 ~ 500 ps。


Jitter is an important subject of research for modern high-speed circuits and data transmission systems. With the increasing data rates of new high-speed I/O and bus standards, the measurement of jitter is rapidly becoming a necessity for ensuring error free digital communication. However, measuring high-speed clock jitters is a difficult task. It usually relies on expensive ATE (automatic test equipment) and usually requires long test time. Furthermore, the situation is getting worse as the trend of system integration onto a single chip continues.
In this thesis, implementation of a jitter measurement infrastructure IP (IIP) is presented. We use FPGA to realize the jitter measurement technique reported in [6]. The BIST technique in [6] measures the RMS value of a Gaussian distribution period jitter. We choose to implement the technique with FPGA because it offers great potential of reuse. With the increasing availability of embedded FPGA, one may program the FPGA to be a jitter measurement circuit, which can be reprogrammed to the desired mission mode function after the jitter measurement is finished. This way, the hardware overhead is minimized.
Finally, to realize a jitter source based on the amplitude to phase conversion method, the AWG (arbitrary waveform generator) Teckronix-AWG520 is employed (RMS jitter: max 668.5 ps and 100Mhz). The jittered signals are applied to the IIP and the measurement results. According to the experimental results, the IIP measure range is 250 ~ 500 ps when the error is less than 10%.


誌謝 I
摘要 II
ABSTRCT III
TABLE OF CONTENTS IV
LIST OF TABLES VI
LIST OF FIGURES VII
CHAPTER 1 INTRODUCTION 1
1.1 THE ROLE OF JITTER 1
1.2 JITTER MEASUREMENT WITH EXTERNAL TEST EQUIPMENT 2
1.3 DFT/BIST TECHNIQUES FOR JITTER MEASUREMENT 3
1.4 THE PROPOSED JITTER MEASUREMENT TECHNIQUE 4
1.5 THESIS ORGANIZATION 5
CHAPTER 2 JITTER DEFINITION 6
2.1 UNDERSTANDING JITTER 6
2.2 TOTAL JITTER [19][20] 10
2.3 JITTER SOURCES [1] 11
CHAPTER 3 JITTER MEASUREMENT METHODOLOGIES 14
3.1 VIEWING JITTER [19] [21] 14
3.2 BIST TECHNIQUES FOR JITTER MEASUREMENT 18
3.2.1 CDF-based method 18
3.2.2 Vernier delay line based method 21
3.3 CHARGE PUMP CIRCUITRY METHOD 24
CHAPTER 4 THE TARGET JITTER MEASUREMENT TECHNIQUE [6] 28
4.1 THE BASIC IDEA 29
4.2 SOLVING THE INVERSE GAUSSIAN CDF 31
4.3 THE BIST ARCHITECTURE 32
4.3.1 BIST circuitry operations 34
4.3.2 Measurement flow 34
4.3.3 An example 35
CHAPTER 5 FPGA IMPLEMENTATION OF THE IIP AND JITTER GENERATION 36
5.1 THE FPGA PLATFORM 36
5.1.1 Features of StratixTM EP1S25F780C6 [23] 36
5.1.2 DC & switching characteristics 38
5.1.3 StratixTM development kits 39
5.2 IIP CIRCUITRY IMPLEMENTATION 41
5.2.1 FPGA implementation 42
5.2.2 Tuning the variable delay line 44
5.3 JITTER GENERATION 46
5.3.1 Amplitude to phase conversion 46
5.3.2 Implementation of the jitter source 47
CHAPTER 6 EXPERIMENATAL RESULTS 55
6.1 EXPERIMENT SETUP 55
6.2 DELAY LINE MEASUREMENT RESULTS 57
6.3 JITTER MEASUREMENT RESULTS 59
CHAPTER 7 CONCLUSIONS 63
REFERENTS 64



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[2]Agilent Technologies, “Jitter solutions for digital circuits,” Application notes. 5988-8427EN
[3]Bernd Laquai, and Ulrich Schoettmer, Angilent Technologies, “A low-cost vectorless ATE-channel architecture for testing high-speed IO signal integrity in high column manufacture,” Application notes.
[4]Jui-Jer Huang, NTUEE, “A Low-Cost Jitter Measurement Technique for BIST Applications,” thesis of master graduated, 2003.
[5]S. Sunter, and A. Roy, “BIST for Phase-Locked Loops in Digital Applications,” Proceeding IEEE International Conference, 1999, pp. 532-540.
[6]Jui-Jer Huang, and Jiun-Lang Huang, “A Low-Cost Jitter Measurement Technique for BIST Applications,” Proceedings of the 12th Asian Test Symposium, 2003, pp. 336-339.
[7]P. Dudek, S. Szczepanski, and J. V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Transactions on Solid-State Circuits,” Vol. 35, No. 2, February 2000, pp. 240-247.
[8]C. C. Tsai and C. L. Lee, “An on-chip jitter measurement circuit for the PLL," in Asian Test Symposium, 2003, pp. 332-335.
[9]A. H. Chan, and G. W. Roberts, “A Synthesizable, Fast and High-Resolution Timing Measurement Device Using a Component-Invariant Vernier Delay Line,” Proceeding IEEE International Test Conference, 2001, pp. 858-867.
[10] S. Tabatabaei, and A. Ivanov, “Embedded Timing Analysis: A SoC Infrastrcture,” IEEE Design & Test of Computers, vol 19, no. 3, May-June 2002, pp. 24-36.
[11] T. Yamaguchi, M. Soma, M. Ishida, T. Watanabe, and T. Watanabe, “Extraction of Peak-to-Peak and RMS Jitter Using an Analytic Signal Method,” Proceeding IEEE VLSI Test Symposium, 2000, pp. 395-402.
[12] T. Yamaguchi, M. Soma, D. Halter, J. Nessen, R. Raina, M. Ishida, and T. Watanabe, “Jitter Measurements of a PowerPCTM Microprocessor using the Analytic Signal Method,” Proceeding International Test Conference, 2000, pp. 955-964.
[13] T. J. Yamaguchi, M. Soma, D. Halter, R. Raina, J. Nissen, and M. Ishida, “A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals,” Proceeding IEEE VLSI Test Symposium, 2001, pp. 102-110.
[14] M. Soma, W. Haileselassie, and J. Sherrid,”Measurement of phase and frequency variationsin radio-frequency signals," in VLSI Test Symposium, 2003, pp. 203-208.
[15] S. Cherubal, and A. Chatterjee, “A High-Resolution Jitter Measurement Technique Using ADC Sampling,” Proceeding IEEE International Conference, 2001, pp. 216-219.
[16] Szplet R., Kalisz J.& Szymanowski R., “Interpolating time counter with 100 ps resolution on a single FPGA device,” IEEE Transactions on Instrumentation and Measurement, Volume: 49 Issue: 4 , Aug. 2000, pp. 879 –883.
[17] Kalisz J., Szplet R., Pelka R & Poniecki A., “Single-chip interpolating time counter with 200-ps resolution and 43-s range,” IEEE Transactions on Instrumentation and Measurement, Volume: 46 Issue: 4, Aug. 1997, pp. 851 –856.
[18] Bernd Laquai and Robert Schneider, Agilent Technologies, “A cost effective method for jitter test of SERDES devices in high volume production,” Application notes.
[19] Tektronix Technology, “Understanding and characterizing timing jitter,” Application notes 55W-16146-1, 2003.
[20] Johnnie Hancock, Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,“ Application note 14488-2, June 2003.
[21] Brian Fetz, Agilent Technologies, “jitter and the new digital regime,” Application note.
[22] Tian Xia and Jien-Chung Lo, “Time-to-voltage converter for on-chip jitter measurement,” IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 6, Dec 2003, pp. 584-589.
[23] Altera Corporation, “Stratix Device Handbook,” manual, S5V1-2.3.
[24] Mozhgan Mansuri, Ali Hadiashar and Chin-Kong Ken Yang, ”Methodology for on-chip adaptive jitter minimization in phase-locked loops,” IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 6, Dec 2003, pp. 371-376.
[25] Gabriele Manganaro, Sung Ung Kwak, S.H. Cho and Anurag Pulincherry, “ A behavioral modeling approach to the design of a low jitter clock source,” IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 6, Dec 2003, pp. 684-687.
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[27] Greg LeCheminant and Johnnie Hancock, “Jitter measurements for high-speed digital transmission,” presented material, April 2003.


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