臺灣博碩士論文加值系統

傳統的直接數位頻率合成器使用在頻率產生器均有顫動的問題，現今解決的方法是利用相位補插來產生正確的脈衝或周期性脈波，使得脈衝出現在正確的時間間隔。
本論文中提出的新架構是先利用相位累加器以及加法器的輸出訊號，在第一階段將電容充電到一個起始電壓，然後第二階段在同一個電容上繼續充電，因此，這種設計可以使得直接數位頻率合成器在每次相位累加器溢位時，都可以修正它的相位誤差，而且在這個設計中，無需使用到ROM Tables來查表所以加快了速度，這個兩階段積分的設計不僅降低了雜訊，也減少了硬體的複雜度。
傳統的數位頻率合成器較為複雜，需要一個ROM來作為相位查表。當數位頻率合成器用來當成時脈產生器時，它本身的顫動問題有可能使系統產生誤動作，而ROM也需要額外的硬體以及更多的能量損耗，為了要克服這些問題，減少硬體的複雜度是很需要的。
在此我們使用了兩種方式來改進傳統的直接數位頻率合成器，兩種方式都無需用到ROM tables，而且在相同的電容上積分。由於使用的是兩段是積分，所以在相位累加器和FSW之間無須再有其他的轉換或計算，這也減低了硬體的複雜度，特別在於相位累加器的資料長度很大的時候，更可以減低硬體的複雜度。此外，因為使用同一個電容的緣故，用來作為補插的延遲時間可以非常精準，而使得輸出沒有顫動的問題。最後也對元件誤差造成的影響作分析，不僅比其它的相位補差數位頻率合成器減少了硬體的複雜度，也有更好的穩定性。

Phase jitter is often a problem when using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator. Most of the existed methods employ phase interpolation to generate a pulse or clock with correct time intervals. In this thesis, a phase-interpolation DDS scheme is proposed, which uses the output of the adder within the phase accumulator to provide an initial voltage on an integration capacitor in the first phase, and then performs an integration operation on the integration capacitor in the second phase. Therefore, this DDS can correct the phase error at each overflow of the phase accumulator. Furthermore, no ROM tables and D/A converters are required, the proposed DDS using a two-phase integration not only provides a jitter-free clock output to reduce its spurious level, but also has a low hardware complexity. Conventional DDS systems are complex in architecture, it requires a ROM lookup table for the phase. While the systems may perform adequately for some applications, jitter is an inherent property of these systems. This is not good because it can lead to low spectral purity causing problems such as system misoperation. Also, ROM lookup tables will cause the larger area requirement and power consumption. Moreover, memory will limit the speed improvement technology migration. To overcome the performance limitations of these systems, it is desirable to provide a simpler system in terms of both architecture and algorithm. Reduction of components makes fabrication simpler and cheaper, and simpler algorithms that do not require use of ROM lookup tables can dramatically simplify the architecture.
To achieve these aims (i.e. a jitter-free clock output), we propose two ROM-less DDS schemes using a two-phase integration that have no D/A converters and no calculations before starting integration, and use the same capacitor and current switching array for two integrations to avoid component value error in circuit implementation. We also analyze the impact caused by the component value errors. The DDS also has lower spurious level, lower hardware complexity, and better stability than other phase-interpolation DDS using two capacitors.

CONTENTS
Chinese Abstract I
English Abstract II
Acknowledgement IV
Contents V
List of Figures VII
Chapter 1 Introduction
1.1 Concept of Frequency Synthesis
1.2 Application of Direct Digital Frequency Synthesizer
1.2.1 Clock generator
1.2.2 FSK encoding
1.2.3 FH spread spectrum and wireless communication
1.3 Motivation and objective
1.4 Organization of the thesis
Chapter 2 DDS’s Algorithm and Architecture
2.1 Basic Theorems of DDS
2.1.1 Conventional DDS
2.2 Existed DDS
Chapter 3 A Jitter-free Phase-interpolation Direct Digital Synthesizer Using Two-phase Integration
3.1 The DDS1
3.1.1 Principles of DDS1
3.1.2 Operation of DDS1
3.1.3 Simulation Results of DDS1
3.2 The DDS2
3.2.1 Principle of DDS2
3.2.2 Operation of DDS2
3.2.3 Simulation Results of DDS2
Chapter 4 Analysis of Component Value Errors
4.1 Direct digital frequency synthesizer with two-capacitor integration
4.1.1 Principles of DDS with two-capacitor integration 4.2 Comparison
4.3 Analyses of Delay Time Error
4.3.1 Delay time error of DDS1
4.3.2 Delay time error of DDS2
4.3.3 Delay time error of DDS with two-capacitor integration
4.4 Analyses of Time Interval Error
4.4.1 Time interval error of DDS1
4.4.2 Time interval error of DDS2
4.4.3 Time interval error of DDS with two-capacitor integration
4.5 Advantage
Chapter 5 Conclusion

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