臺灣博碩士論文加值系統

本文針對電容式溼度感測器設計感測電路，研究中以震盪電路為設計架構，衍生出兩電容式溼度感測器之感測訊號轉換平台，分別為電容轉換頻率與電容轉換電壓。在電容轉換頻率電路中，結合Intel 8254晶片中計時與計數功能設定，利用溼度之變化使電容值產生改變，進而使震盪電路充電、放電週期改變，其輸出頻率隨之改變；在電容轉換電壓電路中，利用相位脈波調變之概念，搭配震盪電路模式設計，經由一互斥或閘比較與邏輯運算後，其脈波寬度大小相對輸出電壓變化。
在溫溼度機操作於25℃以及30~80 %RH變化下，量測得知輸出頻率為6981到6334Hz，在40 %RH時最大誤差為0.18%；輸出電壓為1.21到1.44V，每10 %RH變動0.05V。

This article focuses on capacity type humidity sensors to design sensor circuits and this research adopts oscillator circuits as a design architecture to derive two sensor signal conversion platforms for the capacitance type humidity sensor and these two platforms are capacitance-to-frequency and capacitance-to-voltage converters.
For the capacitance-to-frequency converter circuit, the Intel 8254 chip is integrated in the circuit to count the change of the frequency. For the capacitance-to-voltage converter circuit, the concept of phase pulse modulation is adopted in the oscillator circuit mode design, and the output voltage increases with increase the magnitude of the pulse.
The value of humidity sensor varies from 30 %RH to 80 %RH in the test channel at 25℃, then the frequency is measured between 6334 Hz and 6334Hz. The out voltage in the capacitance-to-voltage converter circuit is varied from 1.21V to 1.44V.

ACKNOWLEDGEMENT Ⅰ
ENGLISH ABSTRACT Ⅱ
CHINESE ABSTRACT Ⅲ
TABLES OF CONTENTS Ⅳ
LIST OF FIGURES Ⅶ
LIST OF TABLES Ⅹ
CHAPTER
1 Preface 1
1.1 Background 1
1.2 Motive 2
1.3 Summary of Chapters and Sections 3 CHAPTER
2 Humidity Sensor Literature Review 4
2.1 Ceramic Humidity Sensor 4
2.2 Electrolyte Humidity Sensor 5
2.3 Polymer Humidity Sensor 6
2.3.1 Resistance Type Humidity Sensor 7
2.3.2 Capacitance Type Humidity Sensor 9
2.4 Capacitance Sensor Signal Processing Circuit 11
2.5 Conclusion 15
CHAPTER
3 Signal Processing Circuit Design 16
3.1 Brief Introduction 16
3.2 Operational Amplifier 18
3.3 Capacitance Conversion Frequency Interface 24
3.4 Capacitance Conversion Voltage Interface 32
3.5 Conclusion 34
CHAPTER
4 Signal Processing Circuit 35
4.1 Operational Amplifier 35
4.2 Simulation and Result of OP Design 40
4.2.1 Frequency Echo 40
4.2.2 Temporary Echo 40
4.2.3 Operational Amplifier Simulation Result 41
4.3 IC Design Flow and Layout Consideration 43
4.3.1 Folded Cascode OP Layout 44
4.3.2 Overall Chip Layout 46
4.4 Capacitance Conversion Frequency Interface 50
4.5 Capacitance Conversion Voltage Interface 61
CHAPTER
5 Result and Conclusion 67
5.1 Integrated Circuit 67
5.2 System Circuit 68
CHAPTER
6 Conclusion and Perspective 70
6.1 Conclusion 70
6.2 Perspective 72
REFERENCE 73
AUTHOR 76

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