臺灣博碩士論文加值系統

根據鎖相回路(PLL)的設計理論，本篇論文設計了由LC振盪器組成的頻率合成器以及利用環形振盪器組成的資料回復器。其中，頻率合成器是應用於802.11a 的標準，電路包括頻率相位檢測器、充電幫浦、迴路濾波器和預除器。高速預除器是採用注入鎖定及米勒除頻器。另外，我們設計一應用於2.488GHz之光纖通訊的資料回復器。其組成部分包括相位檢測器、充電幫浦、迴路濾波器和環形振盪器。我們利用simulink和ADS來模擬此兩種架構在系統及電路層級的特性。這些設計是使用台積電的TSMC 0.18 CMOS 製程、供應電壓為1.8伏特。

Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the frequency synthesizer for 802.11a includes the building blocks such as the phase frequency detector, charge pump, loop filter and prescaler. A high-speed prescaler is designed based on injection-locked and Miller frequency dividers. The implementation of the CDR circuit for 2.488GHz optical communications is also presented. The building blocks of CDR that including phase detector, charge pump, loop filter and VCO are discussed and designed. The circuits are simulated with simulink and ADS to verify the system- and transistor- level performances based on TSMC 0.18um CMOS one-poly six-metal (1P6M) technology with a 1.8V supply.

摘要 I
ABSTRACT II
致謝 III
CONTENTS IV
LIST OF FIGURES VII
LIST OF TABLES XI
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 SYSTEM CONSIDERATION 3
2.1 General Concepts 3
2.1.1 Phase noise 3
2.1.2 Reference spurs 5
2.1.3 Settling time 6
2.2 Phase Locked Loop Architecture 6
2.2.1 System consideration 6
2.2.2 The functional blocks of phase-locked loop 7
2.2.3 Linearized PLL models 8
2.2.3.1 First-order PLL 9
2.2.3.2 Second-order PLL 10
2.2.3.3 Third-order PLL 12
2.2.3.4 Fourth-order PLL 16
2.2.4 Voltage-controlled oscillator (VCO) 18
2.2.5 Phase frequency detector 19
2.2.6 Charge pump and loop filter 22
2.2.6.1 Charge pump 22
2.2.6.2 Loop filter 23
2.2.7 Integer-N divider 26
2.3 PLL Noise Analysis 28
2.3.1 Noise trade-offs in PLL 28
2.3.2 Phase detector dead zone 30
2.3.3 Jitter 31
2.4 Summary 32
CHAPTER 3 DESIGN OF THE U-NII FREQUENCY SYNTHESIZERS 33
3.1 General Concept 33
3.2 General Concepts of a Voltage-Controlled Oscillator 34
3.2.1 The theory of oscillator 35
3.2.2 Inductor 37
3.2.3 Design of the VCO 38
3.2.4 Basic LC tank VCO 39
3.2.5 Complementary crossed-coupled LC-tank VCO 40
3.2.6 Q of LC-tank oscillator 42
3.2.7 Noise sources of LC-tank VCO 43
3.3 High-Speed Prescalers 47
3.3.1 Injection-locked frequency divider 47
3.3.2 Miller frequency divider 51
3.3.3 Simulation results 55
3.3.3.1 VCO Simulation 55
3.3.3.2 High-speed prescalers simulation 57
3.4 Dual-Modulus Prescaler 60
3.4.1 Divide by 8/9 60
3.4.2 Program counter and swallow counter 62
3.4.3 Program counter and swallow counter simulation 63
3.5 Phase/Frequency Detector 65
3.6 Charge Pump and Loop Filter 67
3.7 Close Loop Simulation 69
3.8 Summary 74
CHAPTER 4 DESIGN OF THE OC-48 CLOCK AND DATA RECOVERY CIRCUIT 76
4.1 General Concept 76
4.2 Brief of Random Binary Data 76
4.2.1 Data Format 77
4.2.2 Generation of Random Binary Data 78
4.3 Simple CDR Circuit 79
4.4 Voltage-Controlled Oscillator 80
4.5 The Hogge Phase Detector 81
4.6 Charge Pump and Low-Pass Filter 83
4.7 Simulation 84
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 89
REFERENCES 90

[1] B. Razavi and R. H. Yan, “Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS,” IEEE J.Solid-State Circuits, vol.30, NO. 2, pp. 101-109, Feb. 1995.
[2] B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill,2001.
[3] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor Application Note, no. 1001, May 1996.
[4] B. Chang, J. Park, and W. Kim, “A 1.2GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.
[5] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
[6] Behzad Razavi, “RF Microelectronics,” Upper Saddle River, NJ: Prentice Hall,1998
[7] F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980.
[8] B. Razavi, ed., “Monolithic Phase-Locked Loops and Clock Recovery Circuits,” IEEE Press, Piscataway, NJ 1996.
[9] ESTI, Broadband radio access networks (BRAN); High performance radio local area network (HIPERLAN) type 2; requirements and architectures for wireless broadband access, TS 101 475 v1.1.1, April 2000.
[10] J. Craninckx, and M. Steyaert, “Wireless CMOS Frequency synthesizer Design,” Kluwer Academic Publishers, 1998.
[11] B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill,2001.
[12] A. R. Kral, “A 2.4GHz Frequency Synthesizer in CMOS,” MS thesis, Dept. of Electrical Engineering, University of California Los Angeles, Mar. 1998.
[13] A. Hajimiri and T. H. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE J. Solid-State Circuits, vol.34, no.5, pp. 717-724, May 1999.
[14] M. Tiebout, “Low-Power Low-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS,” IEEE J. Solid-State Circuits, Vol. 36, NO.7, pp.1018-1024, July 2001.
[15] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated-Circuits,” Cambridge University, 1998.
[16] H. R. Rategh and T. H. Lee, “Superharmonic injection locked oscillators as low power frequency dividers”, Symp. VLSI Circuits Dig., pp.132-135, 1998.
[17]R. L. Miller, “Fractional-Frequency generator utilizing regenerative modulation,”Proc. Inst. Radio En. ,vol. 27, pp.446-456,July1939.
[18] J. Lee and B. Razavi, “A 40GHz frequency divider in CMOS technology,” IEEE J. Solid-State Circuits, vol.39, no.4, April 2004.
[19] J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEE J.Solid-State Circuits, vol.24, no. 1, pp. 62-70, February 1989.
[20] H. O. Johanssom, “A Simple Recharged CMOS Phase Frequency Detector,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp.295-299, Feb. 1998.
[21] H. O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE J. Solid-State Circuits, vol. 33, no. 2, February 2000.
[22] W. F. Egan, “Frequency Synthesis by Phase Lock,” Wiley-Interscience.
[23] C. Lam and B. Razavi, “A 2.6/5.2GHz Frequency Synthesizer in CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, no. 5, May 2001.
[24] T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894, June 2003.
[25] J. M. Hsu, “Design and Application of CMOS PLL/DLL,” MS Thesis, Dept. of Electrical Engineering, National Taiwan University, June 1999.
[26] Joonsuk Lee, and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp.1137-1145, Aug. 2000.
[27] C. R. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312–14, Dec. 1985.
[28] J. G. Maneatis, “Precise delay generation using coupled oscillators,” Ph. D. dissertation, Stanford University, June 1994.