跳到主要內容

臺灣博碩士論文加值系統

(100.26.196.222) 您好!臺灣時間:2024/02/23 09:21
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:湯鎮帆
研究生(外文):Chen-Fan Tan
論文名稱:兩倍取樣差和調變器的雜訊降低和模擬模型建立之技巧
論文名稱(外文):Noise Reduction and Simulation Modeling Techniques of the Double-Sampling Delta-Sigma Modulator
指導教授:劉皆成
指導教授(外文):Jie-Chereng Liu
學位類別:碩士
校院名稱:大同大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:109
中文關鍵詞:兩倍取樣差和調變器三角積分器
外文關鍵詞:additive-error switchingbehavior modeldelta-sigmadouble-sampling
相關次數:
  • 被引用被引用:0
  • 點閱點閱:236
  • 評分評分:
  • 下載下載:20
  • 收藏至我的研究室書目清單書目收藏:0
差和調變器是種可以提供高解析度類比轉數位轉換器的方法。有一種兩倍取樣的技術是藉由不改變元件的特性而達成取樣頻率變為原本兩倍的目的,進而增進調變器的效能。不幸的是,因為電路本身電容的不匹配會導致在取樣頻率一半位置處的雜訊會折回到低頻的訊號帶。這篇論文我使用了兩種方法去減少折回的雜訊。第一種方法是將雜訊的轉換函數調整成帶通的形式;第二種是使用數位邏輯電路去控制開關,使雜訊能達到均勻分布的目的。
最後我使用 SMASH 將這兩種方法整合起來模擬,訊號的頻率為10 kHz,取樣頻率為1.28 MHz,超取樣比為128,頻寬為10 kHz。使用TSMC 0.18 um CMOS 1P6M製程,3.3 V供應電壓,在不匹配參數是10% 的情況下,可以達到66.7 dB之訊號雜訊比。
Delta-sigma modulator is a proven method to realize high resolution analog-to-digital converters. A way to implement such a modulator by using double-sampling technique. Unfortunately, capacitors mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. In this thesis, we propose two methods to reduce the folded noise. The first one is modifying the noise transfer function (NTF) into a bandpass form. The other one is by using digital logic circuits to control switches.
Both the proposed methods was integrated and the system was simulated by using SMASH. The input frequency is 10 kHz, the sampling frequency is 1.28 MHz and oversampling ratio is 128. Using TSMC 0.18 um 1P6M 3.3 V process. Under mismatch parameter δ= 10 %, we can achieve peak SNDR about 66.7 dB.
ACKNOWLEDGMENTS Ⅰ
ABSTRACT Ⅱ
CHINESE ABSTRACT Ⅲ
TABLES OF CONTENTS Ⅳ
LISTS OF FIGURES Ⅷ
LISTS OF TABLES ⅩⅣ

CHAPTER 1 INTRODUCTION 1

CHAPTER 2 DELTA-SIGMA MODULATOR FUNDAMENTALS 3

2.1 PCM A/D Conversion 3
2.1.1 Nyquist Rate Conversion 3
2.1.2 Quantization 4
2.1.3 Oversampling Techniques 8
2.2 Noise-Shaped Delta-Sigma Modulator 11
2.2.1 First-Order Noise Shaping 13
2.2.2 Second-Order Noise Shaping 17
2.2.3 Higher-Order Modulator 19
2.2.4 Multibit Modulator 23
2.2.5 Cascaded Modulator 24
2.3 Limit Cycle Oscillation 26
2.4 Idle Tones 28

CHAPTER 3 NOISE REDUCTION OF DOUBLE-SAMPLING ΔΣ MODULATOR 30

3.1 The Fundamental Theory 30
3.2 Modifying the Quantization Noise Transfer Function 36
3.3 Additive-Error Switching 42

CHAPTER 4 BEHAVIORAL MODEL OF SC DELTA-SIGMA MODULATOR 49

4.1 Delta-Sigma Modulator Nonidealities 49
4.1.1 Clock Jitter 50
4.1.2 Thermal Noise of Switches 52
4.1.3 Operational Amplifier Noise 54
4.1.4 Operational Amplifier Nonidealities 55
4.1.4.1 DC Gain 55
4.1.4.2 Slew Rate and Saturation Voltage 56
4.2 Simulation Results 57

CHAPTER 5 CIRCUIT DESIGN OF DOUBLE-SAMPLING ΔΣ MODULATOR 62

5.1 Design and Simulation of Circuit Elements 62
5.1.1 Integrators 66
5.1.2 Operational Amplifier 66
5.1.3 Switches 75
5.1.4 Clock Generator 80
5.1.5 Comparator 81

5.2 Simulation of the Fourth-Order Double-Sampling ΔΣ Modulator 83

CHAPTER 6 CONCLUSIONS 89

REFERENCES 90
[1] A. Oppennheim and R. Schafer, Discrete Time Signal Processing. Prentice-Hall, 1989.
[2] James C. Candy and Gabor C. Temes, Overampling Delta-Sigma Data Converters. IEEE Press, 1991.
[3] David A. Johns and Ken Martin, Analog Integrated Circuit Design. John Wiely & Sons, 1996.
[4] Steven R. Norsworthy, Richard Schrier, and Gabor C. Thems, Delta-Sigma Converters: theory , design and simulation. IEEE Press, 1996.
[5] P. M. Aziz, H. V. Sorensen, and J. V. D. Spiegel, “An overview of delta-sigma converters,” IEEE J. Signal Processing Magazine, pp. 61-84, 1996.
[6] F. Wang and R. Harjani, Design of modulators for oversampled converters. Kluwer Academic Publishers, pp. 1-5.
[7] J. C. Candy, “A use of double integration in sigma-delta modulator,” IEEE ransactions on Communications, vol. COM-33, no. 3, pp. 249-258, March 1985.
[8] K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Transactions on Circuits and Systems, pp. 309-318, March, 1990.
[9] R. Jacob Baker, Harry W. Li, and David E. Boyce, CMOS Circuit Design, Layout, and Simulation. IEEE Press, 1998.
[10] L. Longo and M. Copeland, “The 13 bit ISDN-band oversampled ADC using two-stage third order noise shaping,” IEEE Proceedings of Custom Integrated Circuits Conference, January 1998.
[11] G. Yin, F. Stubbe, and W. Sansen, “A 16-b 320-kHz CMOS A/D converter using two-stage third-order sigma-delta noise shaping,“ IEEE Journal of Solid State Circuits, pp. 640-647, June, 1993.
[12] V. Friedman, “The structure of limit cycles in sigma delta modulation,” IEEE Transactions on Communications, pp. 972-979, August, 1988.
[13] S. Hein and A. Zakhor, “On the stability of sigma delta modulators,” IEEE Transactions on Signal Processing, pp. 2322-2348, July, 1993.
[14] J. C. Candy and O. J. Benjmain, “The structure of quantization noise from sigma-delta modulation,“ IEEE Trans. Commun., vol. COM-29, pp.1316-1323, Sept 1981.
[15] D. A. Johns and K. Martin, Analog Integrated Circuit Design. John Wiley & Sons, New York, 1997.
[16] T. Burmas, K. Dyer, P. Hurst, and S. Lewis, “A second-order double-sampled delta-sigma modulator using additive-error switching,” IEEE J. Solid-State Circuits, vol. 31, pp.284-293, Mar. 1996.
[17] H. Yang and E. ElMasry, “Double sampling delta-sigma modulators,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 524-529, July 1996.
[18] P. Rombouts, J. Raman, and L. Weyten, “An efficient technique to eliminate quantization noise folding in double-sampling ΣΔ modulators,” in Proc. IEEE Int. Symp. Circuits and Systems, vol.3, Phoenix, AZ, May 2002, pp. 707-710.
[19] P. Rombouts, J. Raman, and L. Weyten, “An approach to tackle quantization noise folding in double-sampling ΣΔ modulator,” IEEE Trans. Circuits syst. II, vol. 50, pp. 157-163, Apr. 2003.
[20] Behzad Razavi, Design of Analog CMOS Integrated Circuit. McGraw-Hill, New York, 2001.
[21] D. G. Haigh and B. Singh, “A switching scheme for switch-capacitor filters, which reduces effect of parasitic capacitances associated with control terminal,” Proc. IEEE Int. Symp. On Circuits and Systems, vol. 2, pp. 586-589, June 1983.
[22] D. B. Ribner, R. D. Baertsch, S. L. Garverick, D. T. McGrath, J. E. Krisciunas, and T. Fujii, “A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities,” IEEE J. of Solid-State Circuits, vol. 26, no. 12, pp. 1764-1773, December 1991.
[23] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. The Institute of Electrical and Electronics Engineers, Inc., New York, 1998.
[24] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuit. John Wiely & Sons, 1995.
[25] Behzad Razavi, Principles of Data Conversion System Design. AT&T Bell Laboratories, New York, 1995.
[26] A. Yukawa, “A CMOS 8-bit high speed A/D converter IC,” IEEE J. of Solid-State Circuits, vol. 20, pp. 775-779, June 1985.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top