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研究生:劉偉章
研究生(外文):Wei-Chang Liu
論文名稱:互補金氧半超低電壓高電源拒斥比運算放大器之設計
論文名稱(外文):The Design of Very-Low-Voltage Operational Amplifier with High Power Supply Rejection Ratio
指導教授:李蒼松
指導教授(外文):Tsung-Sum Lee
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:64
中文關鍵詞:電源拒斥比疊接補償中和電路技巧運算放大器
外文關鍵詞:cacode compensationpower supply rejection ratiooperational amplifierneutralization skill
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運算放大器(operational amplifier)在類比電路中是很基本而且很重要的元件。在近幾年來,由於操作電壓一直降低,使得運算放大器的設計變的有挑戰性。且由於混合積體電路的流行,使得數位電路雜訊容易經由電源耦合到類比電路而影響到電路的效能,本論文使用到疊接補償(cascode compensation)的方式來加強電源雜訊的排斥能力。在交換式電容(switch-capacitor)應用電路中,運算放大器的輸入電容會影響到電路整體速度,本文利用中和(neutralization)的技巧來達到較低的輸入電容。一個1.1伏特供應電壓且高電源拒斥比的運算放大器以TSMC0.35μm 2P4M製程實現。
The operational amplifier is the basic and important block in analog circuit. In recent years the supply voltage is scaled down in modern process, it will be a challenge to design the operational amplifier in such low supply voltage. Due to the popularity of mixed-mode integrated circuit design, digital circuit noise can easily couple to analog circuit through power path. A cascode compensation method will be used for enhance analog circuit power supply noise rejection ability. In switch-capacitor application the input capacitor of operational amplifier will affect the speed of whole circuit. A neutralization circuit skill will improve this problem in this thesis. A 1.1 voltage operational amplifier with high power supply rejection ratio is designed in this thesis using TSMC0.35μm 2P4M process .
目錄
摘 要 I
ABSTRACT II
誌謝 III
第一章、緒論 - 1 -
1.1 研究動機 - 1 -
1.2 論文架構 - 2 -
第二章、超低電壓運算放大器 - 3 -
2.1 運算放大器的規格 - 3 -
2.2超低電壓放大器的實現方法與比較 - 12 -
第三章、電路設計 - 17 -
3.1 輸入級電路(INPUT STAGE): - 17 -
3.2共源級放大器電路(COMMON-SOURCE OUTPUT STAGE): - 19 -
3.3頻率補償電路(FREQUENCY COMPENSATION): - 20 -
3.4中和(NEUTRALIZATION)的技巧 - 25 -
3.5其他考量 - 29 -
3.6設計流程 - 34 -
第四章、模擬結果、佈局及量測方法 - 38 -
4.1 模擬結果(SIMULATION RESULTS): - 38 -
4.2 電路佈局: - 46 -
4.3 運算放大器的量測方法 - 50 -
第五章 結論 - 53 -
參考文獻 - 54 -
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[16] Tsumg-Sum Lee, Wei-Chang Liu,and Chu-Teng Chung,2004,“Design Techniques for CMOS Very-Low-Voltage Operational Amplifier with Enhanced Power Supply Rejection Ratio”,accepted by 2004 IEEE Midwest Symposium on Circuit and Systems,Hiroshima,Japan.
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