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研究生:鐘竣騰
研究生(外文):Chun-Teng Chung
論文名稱:低電壓高增益高電源拒斥比互補金氧半運算放大器之研究
論文名稱(外文):The Research of Low-voltage high-gain CMOS operational amplifier with enhanced PSRR
指導教授:李蒼松
指導教授(外文):Tsung-Sum Lee
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:52
中文關鍵詞:電源拒斥比運算放大器高增益低電壓
外文關鍵詞:high-gainLow-voltagePSRRoperational amplifier
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運算放大器使用傳統的米勒電容補償方式無法在高頻獲得良好的電源拒斥比,本論文採用標準的TSMC 0.35μm 2P4M互補式金氧半製程實現一個低電壓高增益高電源拒斥比的運算放大器,藉由使用疊加補償方式對於高頻的電源拒斥比有很大的改善。在低電壓的設計,輸入共模範圍是一個很重要的考量,輸入共模範圍由輸入級所決定,在差動輸入級採用摺疊疊加的主動式負載來增加輸入共模範圍並且達到高增益。此運算放大器採用電容中和的技術,在輸入級可以降低輸入電容以及增加輸入阻抗。藉由這些方法此運算放大器的工作電壓能夠維持在1.2V。
Conventional Miller compensation is used in operational amplifiers and thus suffers from poor power supply rejection ratio at high frequencies , in this thesis , a low-voltage high-gain operational amplifier with enhanced PSRR in standard TSMC 0.35μm 2P4M CMOS process is presented. By using cascode compensation, the resulting power supply rejection ratio (PSRR) at high frequency is greatly improved .A critical aspect in low-voltage design is the input common-mode range, which depends on the input stage. Specifically the differential input stage arranged with a folded-cascode active load has been used to save input swing and achieve high gain .The operational amplifier adopts neutralization capacitors topology for input stage to reduce the input capacitances and increase the input resistance .Using these principles, the operational amplifier has been designed that can operate down to 1.2V.
目 錄

中文摘要 ------------------------------------------------------------------------------ i
英文摘要 ------------------------------------------------------------------------------ ii
誌謝 ------------------------------------------------------------------------------ iii
目錄 ------------------------------------------------------------------------------ iv
表目錄 ------------------------------------------------------------------------------ v
圖目錄 ------------------------------------------------------------------------------ vi

第一章 緒論 1
1.1 研究動機------------------------------------------------------------------ 1
1.2 研究目標------------------------------------------------------------------ 3
1.3 內容大綱------------------------------------------------------------------ 4
第二章 低電壓電路設計考量 5
2.1 互補金氧半電晶體的電氣特性--------------------------------------- 5
2.1.1 強反轉區------------------------------------------------------------------ 5
2.1.2 弱反轉區------------------------------------------------------------------ 8
2.2 結論-------------------------------------------------------------------------- 9
第三章 電路設計與模擬 10
3.1 高輸出擺幅電流鏡------------------------------------------------------ 10
3.2 輸入級--------------------------------------------------------------------- 13
3.2.1 差動輸入級------------------------------------------------------------- 13
3.3 電容中和------------------------------------------------------------------ 17
3.4 共源級輸出級------------------------------------------------------------ 19
3.5 低電壓摺疊疊加運算放大器之設計--------------------------------- 20
3.6 測試電路配置與模擬結果--------------------------------------------- 29
第四章 電路佈局及佈局平面圖 40
4.1 佈局的考量--------------------------------------------------------------- 40
4.2 佈局平面圖--------------------------------------------------------------- 44
第五章 結論與未來研究方向 46
參考文獻 ------------------------------------------------------------------------------ 47
附錄一 圖3.8之轉移函數分析------------------------------------------------- 49
參 考 文 獻

[1] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Designing 1-V op amps using standard digital CMOS technology, ” IEEE Trans. Circuits and Systems II, vol. 45, pp. 769-780, July 1998.
[2] J. F. Duque-Carrillo, J. L. Ausin, G. Torelli, J. M. Valverde, and M. A. Dominguez, “1-V rail-to-rail operational amplifiers in standard CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 33-44, 2000.
[3] G. Giustolisi, G. Palmisano, G. Palumbo, and T. Segreto, “1.2-V CMOS op-amp with a dynamically biased output stage,” IEEE J. Solid-State Circuits, vol. 35, pp. 632-636, April 2000.
[4] E. K. F. Lee, “Low-voltage opamp design and differential difference amplifier design using linear transconductor with resistor input,” IEEE Trans. Circuits and Systems II, vol. 47, pp. 776-778, Aug. 2000.
[5] T. Lehmann and M. Cassia, “1-V power CMOS cascode amplifier,” IEEE J. Solid-State Circuits, vol. 36, pp. 1082-1086, July 2001.
[6] T. Stockstad and H. Yoshizawa, “A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier,” IEEE J. Solid-State Circuits, vol. 37, pp. 286-292, March 2002.
[7] W. C. Black, D. J. Allstot, and R. A. Reed, “A high performance low power CMOS channel filter,” IEEE J. Solid-State Circuits, vol. 15, pp. 929-938, Dec. 1980.
[8] P. R. Gray and R.G. Meyer, “MOS operational amplifier design – a tutorial overview,” IEEE J. Solid-State Circuits, vol. 17, pp. 969-982, Dec. 1982.
[9] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons, Inc., 1986, pp. 220-221.
[10] R. Gregorian, Introduction to CMOS Op-amps and Comparators, John Wiley & Sons, Inc., 1999, pp. 315-316.
[11] B. K. Ahuja, “An improved frequency compensation technique for CMOS operational amplifier,” IEEE J. Solid-State Circuits, vol. 178, pp. 629-633, Dec. 1983.
[12] P. R. Gray, P. J. Hurst, S.H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed., pp. 849-850, 2001.
[13] J. A. Mataya, G. W. Haines, and B. S. Marshall, “IF amplifier using compensated transistors,” IEEE J. Solid-State Circuits, vol. 3, pp. 401-407, Dec. 1968.
[14] P. J. Hurst , S. H. Lewis J. P. Keane, F. Aram, and K. C. Dyer, “Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers,” IEEE Trans. Circuits and Systems I, vol. 51, pp. 275-285, Feb. 2004.
[15] J. N. Babanezhad and R. Gregorian, “A programmable gain/loss circuit,” IEEE J. Solid-State Circuits, vol. 22, pp. 1082-1089, Dec. 1987.
[16] Andrew M. Abo and Paul R. Gray,"A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter ",IEEE Journal of Solid-State Circuits ,Vol. 34 ,No.5,pp.599-606,May 1999.
[17] Behzad Razavi. “Design of Analog CMOS Integrated Circuits.” McGraw-Hill, 2000.
[18] R.Hogervorst, J.P.Tero, R.G.H.Eschauzier, J.H.Huijsing, “A Compact Power - Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VSLI Cell Libraries” pp. 1505-1513, IEEE J. Solid-State Circ.,vol.29, no. 12, december 1994
[19] Ron Hogervorst, and Johan H. Huijsing, “Design of Low-Voltage, Low-Power Operational Amplifier Cells,” Kluwer Academic Publishers, 1996.
[20] Tsung-Sum Lee, Wei-Chang Liu, and Chun-Teng Chung, 2004, “Design Techniques for CMOS Very-Low-Voltage Operational Amplifiers with Enhanced Power Supply Rejection Ratio,“ accepted by 2004 IEEE Midwest Symposium on Circuits and Systems, Hiroshima, Japan.
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