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研究生:黃于芸
研究生(外文):Yu-Yun Huang
論文名稱:10位元50MHz取樣頻率之CMOS管流式類比數位轉換器
論文名稱(外文):10-bit 50MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter
指導教授:許明華許明華引用關係
指導教授(外文):Ming-Hwa Sheu
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:72
中文關鍵詞:轉換器積體電路管流式類比數位轉換器類比
外文關鍵詞:VLSIconverterAnalogA/DADCpipeline
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在現今許多的應用當中,大多使用數位信號處理技術來處理所傳輸的資料,因此,在接收到的類比訊號及數位信號處理系統之間,就需要將類比訊轉換成數位訊號的介面。由於近年來無線通訊系統和個人可攜式電子產品的成長,對於低功率的電路也有著不可或缺的需求。在許多種類的CMOS類比數位轉換器的架構中,由於管流式類比數位轉換器每一級的取樣保持電路如同快閃式類比數位轉換器一樣能同時的動作,因此管流式類比數位轉換器能達到高速的輸入性能和快速的處理能力。在本論文中,針對高速度的管流式類比數位轉換器做設計,並且在設計過程中盡可能的減低消耗功率。
在本論文中,使用台積電標準0.25微米互補式金氧半製程設計與實現一個十位元,50MHz取樣頻率的CMOS管流式類比數位轉換器,每一個階段為1.5位元的解析度。根據模擬結果,整體電路在50MHz的取樣頻率下SNDR為58.26dB,可達10位元的精確度,消耗功率為136.8mW,整體電路佈局面積為1050×845um2。
Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and the DSP system. With the explosive growth of wireless communication systems and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can achieve good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each stage. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipation as well.
In this thesis, a 10-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been succeddfully designed and implemented using the TSMC 0.25μm CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 58.26dB signal-to-(noise+distortion) ration - conforming to the 10-bit accuracy, and the estimated power dissipation is about 136.8 mW. Total layout area is about 1050×845um2.
中文摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
Chapter 1 緒論 1
1.1 研究動機 1
1.2 類比數位轉換器種類簡介 1
1.3 論文架構 3

Chapter 2 研究背景 4
2.1 簡介 4
2.2 類比數位轉換器之架構介紹 4
2.2.1 快閃式類比數位轉換器(Flash ADC) 4
2.2.2 兩階段式類比數位轉換器(Two-Step ADC) 6
2.2.3 管流式類比數位轉換器(Pipelined ADC) 6
2.2.4 循環式類比數位轉換器(Cyclic ADC) 7
2.3 管流式類比數位轉換器電路動作分析 8
2.4 數位錯誤修正技術(Digital error correction technique) 11
2.5 類比數位轉換器之特性參數 13
2.5.1 解析度(Resolution) 14
2.5.2 最小步階數(LSB, Least significant bit) 14
2.5.3 訊號對雜訊比(SNR, Signal to noise ratio) 14
2.5.4 訊號對雜訊及失真比(SNDR, SNR+Distortion ratio) 16
2.5.5 等效位元數目(ENOB, Effective number of bits) 16
2.5.6 非線性(Nonlinearity) 16

Chapter 3 管流式類比數位轉換器之分析 19
3.1 簡介 19
3.2 開關式電容電路(Switch capacitor circuit) 19
3.2.1 MOS開關電阻 19
3.2.2 電荷注入效應(Charge injection) 21
3.2.3 拔靴帶式電路(Bootstrapped circuit) 23
3.2.4 時脈滲入效應(Clock feed-through) 24
3.3 Pipeline ADC特性模擬(Use Matlab) 25

Chapter 4 管流式類比數位轉換器之設計與分析 31
4.1 簡介 31
4.2 1.5Bits/Stage Pipelined ADC架構說明 31
4.3 運算放大器(OPA) 32
4.4 取樣保持電路(S/H, Sample and hole circuit) 35
4.5 子類比數位訊號轉換器電路(Sub-ADC) 37
4.5.1 比較器電路(Comparator) 37
4.5.2 子類比數位訊號轉換器(Sub-ADC) 39
4.6 DAC/減法器/增益級電路(MDAC) 40
4.7 暫存器電路(D型正緣觸發暫存器) 43
4.8 數位錯誤修正電路(Digital error correction) 45
4.9 時脈產生器 46
4.10 九級管流式類比數位轉換器 47

Chapter 5 管流式類比數位轉換器之佈局考量 49
5.1 簡介 49
5.2 類比電路佈局考量 49
5.3 管流式類比數位轉換器之佈局 52

Chapter 6 結論 57
6.1 結論 57
6.2 未來研究方向 57
Reference 參考文獻 58
Autobioarphy 自傳 61
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