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研究生:吳康碩
研究生(外文):Kang-Shuo Wu
論文名稱:迴旋解碼與SOVA基礎渦輪解碼之FPGA實現
論文名稱(外文):FPGA Implementation of Convolutional and SOVA-Based Turbo Decoder
指導教授:連振凱連振凱引用關係
指導教授(外文):Jenn-Kaie Lain
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:中文
論文頁數:63
中文關鍵詞:渦輪解碼FPGA迴旋解碼
外文關鍵詞:Convolutional DecoderTurbo DecoderFPGA
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渦輪碼由於具有相當接近傳輸極限的錯誤更正效能,因此被廣泛地建議採用於第三代的通訊系統中。渦輪碼的解碼架構主要由兩個解碼器元件以及交錯器與反交錯器組成,解碼元件是軟式輸入軟式輸出的架構主要可以分為兩種:一是最大事後機率(Maximun A-Posteriori, MAP)演算法其有極佳的解碼效能,但計算複雜,不容易實現;渦輪編碼器的架構由迴旋編碼器並行串接而來,因此迴旋碼的解碼方式─維特比演算法便成為研究的基礎,傳統的維特比演算法可以改進成具備軟式輸出維特比演算法。由於其計算複雜度不高且具備良好的效能,本論文以FPGA來實現迴旋解碼與軟輸出維特比演算法渦輪解碼,並以Altera Quartus II為設計工具將迴旋解碼與SOVA基礎渦輪解碼實現在Stratix EP1S80元件上。
With the rapidly developing in communication systems, the turbo code is widely used in the third generation communication system owing to its excellent decoding performance. The turbo decoding architecture is composed of two component decoders, an interleaver and a deinterleaver. The component decoder is soft-input soft-output module which can be classified into two categories: one is the maximum a-posteriori (MAP) algorithm that exhibits excellent performance, but is too complex to implement; the other is the soft output Viterbi algorithm (SOVA) evolved from the Viterbi algorithm with the same axiom, as the turbo code is evolved from convolutional code. The thesis then implements the convolutional and SOVA-based turbo decoders with the Altera QuartusII on Stratix EP1S80 device.
摘要 i
ABSTRACT ii
目錄 iii
表目錄 v
圖目錄 vi
第一章 緒論 1
第二章 迴旋碼與渦輪碼 4
2.1 迴旋碼 4
2.2 渦輪碼 10
第三章 解碼演算法 21
3.1 維特比演算法 21
3.2 渦輪碼疊代解碼架構 24
3.3 最大事後機率演算法 26
3.4 軟式輸出維特比演算法 33
第四章 FPGA實現迴旋與渦輪解碼 38
4.1 FPGA實現概要 38
4.2 維特比演算法實現 40
4.3 軟式輸出維特比演算法實現 52
4.4 軟式輸出維特比演算法基礎渦輪解碼 58
第五章 結論 60
參考文獻 61
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[5] J. Hagenauer, and P. Hoeher, “A Viterbi algorithm with soft-decision outputs and its applications,” IEEE GLOBECOM, vol. 3, pp.1680-1686, Nov. 1989.
[6] A. Viterbi, “Error Bounds for Convolutional Codes and Asymptotically Optimum Decoding Algorithm,” IEEE Transactions on Information Theory, pp. 260-269, Apr. 1967.
[7] C. Berrou, P. Adde, E. Angui, and S. Faudeil, “A low complexity soft-output Viterbi decoder architecture,’’ IEEE International Conference on Communications, vol. 2, pp.737-740, May 1993.
[8] J.P. Woodard, and L. Hanzo, “Comparative Study of Turbo Decoding Techniques: An Overview,” IEEE Transactions on Vehicular Technology, vol. 49, no. 6, pp. 2208-2233, Nov. 2000.
[9] M. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. Davis, G. Woodward, C. Nicol, and R. Yan, “A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1555-1564, Nov. 2002.
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[11] O. Joeressen, M. Vaupel, and H. Meyr, “Soft-output Viterbi decoding: VLSI implementation issues,” IEEE 43rd Vehicular Technology Conference, pp.941-944, May, 1993.
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