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研究生:邵朝文
研究生(外文):Thao-wen Shao
論文名稱:可演化式學習之硬體實作及在圖形辨別上的應用
論文名稱(外文):An Implementation of An Evolvable Hardware And Application To Pattern Recognition
指導教授:陳重臣陳重臣引用關係
指導教授(外文):Jong-Chen Cnen
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:資訊管理系碩士班
學門:電算機學門
學類:電算機一般學類
論文種類:學術論文
畢業學年度:92
語文別:中文
論文頁數:84
中文關鍵詞:ANM系統演化式學習FPGA
外文關鍵詞:FPGAevolvable hardwareANM system
相關次數:
  • 被引用被引用:1
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人工類分子神經系統 (Artificial NeuroMolecular System, ANM系統) [Chen, 1993]是一個具有自我組織學習能力的多層類神經資訊處理腦系統。早期的研究是將ANM系統從過去電腦模擬轉成數位電路來實作,但由於ANM系統的數位電路現在仍需透過電路軟體模擬,所以會耗費相當的電腦執行時間,因此本研究目的是將ANM系統以FPGA來建構實際硬體電路,使ANM系統在硬體電路也能快速自我組織與學習能力。
本研究根據ANM系統運作原理建構數位式電路,以Altera 公司開發的FPGA實驗板,將建構完成之電路載入至FPGA上,並進行相關硬體電路的驗證是否符合期望的功能。之後,研究中設計兩個實驗進行實際硬體的測試,經實驗結果顯示,證明建構於FPGA上的ANM系統具有快速學習能力與自我組織學習,且擁有很好的容錯能力處理空間的干擾。
Artificial neuromolecular system (ANM) is a self-organizing learning, multilevel neuromolecular information processing model. An earlier study is to implement it on digital circuits, but it is still a computer simulation model. However, it is time-consuming to perform computer simulation of the mode. The objective of this study is to fully implement the model on on FPGA chip. The implementation of this model on Hardware circuits has significant self-organizing learning.
The model implemented on digital circuits was tested on the Altera Emulation Board. Two experiments were performed. The experiment result showed that the Hardware system has good learning capability. Finally, the Hardware system demonstrated good tolerance capability in dealing with spatial noises.
摘 要 i
ABSTRACT ii
致 謝 iii
目 錄 iv
圖目錄 vi
表目錄 ix
一、 緒論 1
1.1 研究背景與動機 1
1.2 研究目的 2
1.3 研究流程 3
二、 文獻探討 4
2.1 類神經網路 4
2.2 演化式硬體(Evolvable Hardware,EHW) 5
2.2.1 演化式硬體介紹 5
2.2.2 演化的分類 6
2.2.3 演化式硬體評估 7
2.3 ANM系統 8
2.4 FPGA簡介 13
2.4.1 FPGA硬體架構 14
2.4.2 FPGA功能評估 15
2.4.3 FPGA設計流程 16
三、 研究架構 18
3.1 電路架構簡介 18
3.1.1 單元處理PU電路 18
3.1.2 資訊處理神經元(DCN)電路圖 21
3.2 軟、硬體介紹 23
3.2.1 軟體介紹 23
3.2.2 硬體介紹 25
3.3 實驗系統架構 29
3.4 硬體電路實作與測試 32
3.4.1 電路實作與測試流程 32
3.4.2 PU電路硬體實作測試結果 32
3.5 資訊處理神經元DCN電路實作 38
3.5.1 DCN電路編譯(Compiler)與時序分析(Time Analyzer) 38
3.5.2 DCN電路I/O配置Pins Assignment 39
3.5.3 DCN電路模擬(Simmulation) 41
四、 實驗設計與結果 42
4.1 實驗架構 42
4.1.1 Altera實驗板 44
4.1.2 資料轉換 44
4.1.3 同步控制 45
4.2 實驗說明 46
4.3 實驗一:四組圖形於三種不同DCN電路學習 46
4.3.1 適應值計算 49
4.3.2 實驗一訓練結果 49
4.4 實驗二:十個圖形學習 52
4.4.1 實驗二訓練結果 53
4.4.2 實驗二測試實驗 55
4.4.3 實驗二測試結果 57
五、結論與建議 63
5.1 未來研究與建議 64
参考文獻 65
附錄A PU各元件電路實際硬體實作測試波形圖 70
[英文]

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[中文]

[1]林侑賢,2003,可演化學習的多層類分子時經系統之數位電路建構,國立雲林科技大學,碩士論文。
[2]歐謙敏,2001,CPLD數位系統設計,台科大圖書公司出版,台北。
[3]陳重臣,1998,”類分子神經系統的長期進化式學習及計算式適應性研究 Investigation of an Artificial Neuromolecular Architecture on Perpetual Evolutionary Learning and Computational Adaptability”,國科會專題研究計畫。
[4]陳瑞東,2001,以數位電路建立一個具有自主學習能力之ANM硬體架構,國立雲林科技大學,碩士論文。

[參考網站]

[1]Altera,
http://www.altera.com/index.jsp#
[2]Altera, (2004, March). “APEX 20K Programmable Logic Device Data Sheet” [PDF]. Retrieved from: http://www.altera.com/products/devices/apex/apx-index.html
[3]Altera, (2004, February). “Introduction to QuartusII” [PDF]. Retrieved from: http://www.altera.com/support/software/quartus2/licensing/lic-qii_q_and_a.html
[4]CIC, 國家晶片設計中心,
http://www.cic.org.tw/cic_v13/
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