臺灣博碩士論文加值系統

在覆晶封裝（Flip Chip Package，FP）製程中，三維量測對錫鉛凸塊（Solder bump）的製造相當重要。基於X射線（X-ray）或雷射掃瞄（Laser scanning）方法的精密三維量測系統，不僅建置成本高，且系統校正耗時費力。本研究針對覆晶封裝元件之品質檢測，改進一個建置成本低、量測效益高之三維光學量測系統，以快速量測覆晶凸塊高度值，並重建物體表面輪廓圖。
本研究採用顏旭男【2004】所發展以DLP（Digital Light Processing）為基之相位移三維量測系統，並加以改善。主要針對正弦條紋影像進行中值濾波以降低量測之變異，並以矩陣系統參數值取代固定之系統參數值，可隨量測位置的不同而調整此系統參數值，以有效提昇量測之精度；最後經由所量測出每顆凸塊的高度，做一共平面度的檢驗。
由於本研究採用全場量測方式（面掃瞄），量測速度快，可在1秒內完成計算一張640×480像素影像的高度量測。由覆晶凸塊的實驗結果顯示本系統在覆晶錫鉛凸塊的品質檢測上有良好功效，其量測之精度可達2微米。

In flip chip packaging processes, three-dimensional (3D) measurement is important for the quality inspection of solder bumps. Currently, 3D measurements of solder bumps are mainly performed by laser-based systems. They suffer from high equipment cost, and low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3D measurement system improved from Yen and Tsai [2004] is used for the inspection of flip chip solder bumps.
The full-field 3D measurement system adopted in this research is based on a phase shift technique, in which the phase is efficiently and effectively shifted by a software-controlled grating using a digital light processing (DLP) unit. To improve the system proposed by Yen and Tsai, a 2D median filter is first applied in the projected sinusoidal fringe pattern image. The smoothing process can effectively remove optical noise and, therefore, increase the measurement repeatability. Further, the measurement accuracy of the 3D system is determined by a system parameter, which was originally a fixed value in the Yen and Tsai’s configuration. In this research, adaptive parameter values, instead of a fixed value, are employed to improve the measurement accuracy. The system parameter values are prestored in a matrix, and adaptively vary according to the measurement positions. It significantly improves the accuracy of measured heights. After the height of every solder bump is determined, two coplanarity measures of flip chip solder bumps are also proposed in this research. Experimental results from a number of flip chip samples have shown the efficacy of the improved scheme. The computing time of the proposed 3D measurement system for an image of 640×480 pixels is less than 1 seconds, and the measurement accuracy is around 2 μm.

中文摘要………………………………………………………………………. I
目錄……………………………………………………………………………. II
表目錄………………………………………………………………………… IV
圖目錄…………………………………………………………………………. V
第一章 緒論…………………………..………………………………………. 1
1.1 研究背景與動機………………………………………………... 1
1.2 研究範圍與目的………………………………………………... 2
1.3 研究方法簡介…………………………………………………... 3
1.4 論文架構………………………………………….…………….. 4
第二章 文獻回顧…………………………..…………………………………. 5
2.1 BGA與覆晶之瑕疵檢測……………………………………. …. 5
2.2 三維量測技術……………………………………….………….. 7
2.3 相位移量測技術……………………………………….……….. 9
第三章 以DLP為基之相位移三維量測技…….………. ………….………. 11
3.1 相位移量測技術……………………………………………... 11
3.2 數位相位移投射系統…………………………………………... 15
3.3 系統架構………………………………………………………... 18
3.4 系統量測流程……………..……………………………………. 21
3.5 系統參數k值校正……………………………………………... 23
3.6 正弦影像雜訊之濾除….…………………………………..…... 27
3.6.1 中值濾波器之使用…………………..…….………..….... 27
3.6.2 使用中值濾波器實驗結果…………………………..….... 30
第四章 覆晶封裝凸塊高度量測及共平面度檢測...…………………………
4.1 表面黏著技術製程簡介………………………………………... 34
4.2 覆晶封裝製程及其瑕疵…………………..………..…………. 36
4.3 系統架構……………………………………………..….……... 39
4.4 覆晶凸塊高度實驗結果……………………………………….. 40
4.4.1 條紋對比度閥值的選擇……………..…….………..….... 41
4.4.2 覆晶凸塊之高度計算………………..…….………..….... 45
4.4.3 程式之執行時間………………..…….………….……….. 58
4.4.4 檢測覆晶凸塊之共平面性……………………………….. 64
4.5 實驗結論與使用之建議………………………………………... 72
第五章 貢獻與後續研究………………………………….…………….……. 73
5.1 結論………….………………………………………………….. 73
5.2 未來研究方向.………………………………………………….. 74
參考文獻……………………………………………………..……………..…. 76
附錄A 不同材質系統參數k值比較…….………………………………….. 80
附錄B 系統參數k值不同時所造成量測高度之差異 81
附錄C 使用矩陣系統參數值之假設檢定驗證…….…..…………………… 83
附錄D 對正弦條紋使用中值濾波之假設檢定驗證………………………… 84
附錄E 使用固定參數值量測結果（使用白平衡板當參考平面）…………. 85
附錄F 使用矩陣參數值量測結果（使用白平衡板當參考平面）…………. 86
附錄G 使用固定參數值量測結果（使用金屬塊規當參考平面）…………. 87
附錄H 使用矩陣參數值量測結果（使用金屬塊規當參考平面）…………. 88
附錄I 程式介面的設計….……………………………...…. ………………. 89
附錄J 圖4-23中所有凸塊高度…….…………………. …………………… 91
附錄K 圖4-23中凸塊到迴歸平面高度差值………………. ………………. 92
附錄L 程式碼…….………..……………. ………….…………………. …… 93

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