臺灣博碩士論文加值系統

隨著電子產品的開發速度越來越快，漸漸的產品的發展成本已轉向反映到測試成本上，唯有縮短產品的測試時間才能搶得市場先機。想要降低測試成本，可以從減少測試時間著手。藉由安排測試元件的先後順序可以減少整體的測試時間。我們將這種安排系統元件之測試先後順序的方式稱為測試排程。一個有效率的測試排程法可以減少整個系統的測試時間，避免測試時所發生的資源衝突問題，並限制住測試模式時所消耗的電能。本篇論文的目的在於提出一個有效的方法，讓尖峰電能發生的時間錯開來，使得系統晶片能在固定的電能下，縮短測試時間。本論文提出了一個改良過的電能近似模型，稱之為三個局部尖峰電能近似模型。透過這樣的電能近似模型，可以使得測試排程的安排上更有彈性，在結合以電能為主要限制條件的測試排程演算法，以達到較高測試平行度進而縮短整個系統晶片的測試時間。

The cost of developing electronic systems is increasing and a significant part of the cost is related to the testing of the system. Testing cost reduction can be achieved by minimizing the testing time of the system. Efficiently ordering the execution of the tests will minimize the total testing time. This so-called test scheduling determines the order of the execution of the test sets for a system. Efficient test schedules can minimize the overall system application time, avoid test resource conflicts, and limit power dissipation during test mode. The purpose of this thesis is to propose an interleaving scheme under the constraint of fixed power value to minimize the SOC testing time. Therefore, an improved version of the power profile model with less peak power overlap, and a three local peak power approximation model, are thus proposed. Experimental results show the approach proposed in this thesis is efficiently. Comparing to the approaches in [7] and [12], the proposed approach obtains lower testing time for the most cases in SOC d695 benchmark.

書名頁……………………………………………………………… I
授權書……………………………………………………………… II
論文口試委員會審定書…………………………………………… V
中文摘要…………………………………………………………… VII
英文摘要…………………………………………………………… IX
誌謝………………………………………………………………… XI
Contents…………………………………………………………… XII
List of Figures………………………………………………… XIII
List of Tables…………………………………………………… XIV
Symbol Definitions ……………………………………………… XV
Chapter 1.Introduction………………………………………… 1
Chapter 2.Related Work………………………………………… 3
Chapter 3.Proposed Approach……………………………………6
3.1 Scan Cell Design………………………………6
3.2 Test Vector Reordering with power interleaving scheme……………… 8
3.3 Power Constrained Test Scheduling using power interleaving scheme……13
3.4 Case Study……………………………………14
Chapter 4.Experimental Results………………………………18
Chapter 5.Conclusions……………………………………………20
References……………………………………………………………21

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