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[1] T. Xiao, C. W. Chang, and M. M. Sadowska, “Efficient Static Timing Analysis in Presence of Crosstalk,” Proc. 13th IEEE International Conference, on ASIC/SOC, Arlington, VA, Sep. 2000, pp. 335-339. [2] B. Franzini, C. Forzan, D. Pandini, P. Scandolara, and A. D. Fabbro, “Crosstalk Aware Static Timing Analysis: a Two Step Approach,” Proc. Int. Sym. Quality Electr. Design, Mar. 2000, pp. 499-503. [3] K. Hirose and H. Yasuura, “A Bus Delay Reduction Technique Considering Crosstalk,” Proc. Design, Automation and Test in Europe, Paris, March 2000, pp. 441-445. [4] C.J. Alpert, A. Devgan and S.T. Quay, “Buffer insertion for noise and delay optimization,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 18, Issue: 11, Nov.1999 [5] C. Alpert and A. Devgan, “Wire segmenting for Improved Buffer Insertion,” Design Automation Conference, 1997. Proceedings of the 34th, June 9-13, 1997 Pages:588-593 [6] S. Dubey and J. Jorgenson, “Crosstalk reduction using buffer insertion,” Electromagnetic Compatibility, 2002 IEEE International Symposium on, Volume:2, 19-23 Aug. 2002 Pages:639 — 642 vol.2 [7] Eun-Gu Jung; Byung-Soo Choi; Dong-Ik Lee, “High performance asynchronous bus for SoC,” Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on , Volume: 5 , 25-28 May 2003 Pages:V-505 - V-508 vol.5 [8] Lajolo, M.; Reorda, M.S.; Violante, M., “Early evaluation of bus interconnects dependability for system-on-chip designs,” VLSI Design, 2001. Fourteenth International Conference on , 3-7 Jan. 2001 Pages:371 — 376 [9] Cuviello, M.; Dey, S.; Xiaoliang Bai; Yi Zhao, “Fault modeling and simulation for crosstalk in system-on-chip interconnects,” Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on , 7-11 Nov. 1999 Pages:297 — 303 [10] N. Itazaki, Y. Matsumoto, and K. Kinoshita, “An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits,” Proc. 6th Asian Test Symposium, Nov. 1997, pp. 22-27. [11] A. Rubio, N. Itazaki, X. Xu, and K. Kinoshita, “An approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits,” IEEE Trans. on CAD, vol. 13, no. 3, pp. 387-395, March 1994. [12] X. Bai, S. Dey, and J. Rajski, “Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects,” Proc. 37th Design, Automation Conf., Los Angeles, CA, June 2000, pp. 619-624. [13] K. Hirose and H. Yasuura, “A Bus Delay Reduction Technique Considering Crosstalk,” Proc. Design, Automation and Test in Europe, Paris, March 2000, pp. 441-445. [14] H. Zhou and D. F. Wang, “Global routing with crosstalk constrains,” Proc. 35th Design Conf., San Francisco, CA, June 1998, pp. 374-377. [15] P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggemeyer, and T. W. Williams, “Signal integrity Problem in Deep Submicron Arising from Interconnects Between Cores,” Proc. 16th VLSI Test Symp., Monterey, CA, April 1998, pp. 28-33. [16] X. Bai, S. Dey and J. Rajski, “Self-Test Methodology for At-Speed Test of Crosstalk in Chip interconnects,” Proc. Design Automation Conf., Los Angeles, CA, 2000, pp. 619-624. [17] T. Xiao, C. W. Chang, and M. M. Sadowska, “Efficient Static Timing Analysis in Presence of Crosstalk,” Proc. 13th IEEE International Conference, on ASIC/SOC, Arlington, VA, Sep. 2000, pp. 335-339. [18] M. A. Margolese and F. J. Ferguson, “Using Temporal for Eliminating Crosstalk Candidates for Design and Test,” Proc. 17th IEEE VLSI Test Symposium, Dana Point, CA, Apr. 1999, pp. 80-85. [19] B. Franzini, C. Forzan, D. Pandini, P. Scandolara, and A. D. Fabbro, “Crosstalk Aware Static Timing Analysis: a Two Step Approach,” Proc. Int. Sym. Quality Electr. Design, Mar. 2000, pp. 499-503. [20] L. Chen, X. Bai and S. Dey, “Testing for Interconnects Crosstalk Defeats Using On-Chip Embedded Processor Cores,” Proc. Design Automation Conf., Las Vegas, Nevada, Jun. 2001, pp.317-322. [21] W. C. Lai, J. R. Huang, and K. T. Cheng, “Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses,” Proc. VTS. Conf., Marina Del Rey, CA, Apr. 2001, pp. 204-209. [22] K. Sekar, and S. Dey, “LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects,” Proc. VTS. Symposium, 2002, pp. 417-422. [23] M. Favalli and C. Metra, “Bus Crosstalk Fault-Detection Capabilities of Error-Detecting Codes for On-Line Testing,” IEEE Trans. on VLSI, vol. 7, no. 3, pp. 392-396, Sep. 1999. [24] M. Favalli and C. Metra, “Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors,” Proc. Design, Automation and Test in Europe, Munich, Germany Mar. 2001, pp. 290-296. [25] X. Bai and S. Dey, “High-level Crosstalk Defect Simulation for System-on-Chip Interconnects,” Proc. 19th VLSI Test Symposium, Los Angle, CA, Apr. 2001, pp. 169-175. [26] N. Itazaki, Y. Matsumoto, and K. Kinoshita, “A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits,” Proc. Fault Tolerant Computing Symposium, Sendai, Japan 1996, pp. 38-43. [27] K. Chakrabarty, “Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming,” Proc. IEEE VLSI Test Symp., 2000, pp.127-134. [28] Jun Yang, Chen Hu, Youhua Shi, Zhe Zhang, and Longxing Shi, “A New Self-test Structure for At-speed Test of Crosstalk in SoC Busses,” Proc. 4th ASIC, International Conf., Shanghai, China 2001, pp. 631036. [29] Chakraborty, K.; Long, D.E.; Fishburn, J.P.; Singhal, K.; Lun Ye; Ortiz, C., “A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization,” Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 , 12-15 May 2002 Pages:23 — 26 [30] Junmou Zhang; Friedman, E.G, “Crosstalk noise model for shielded interconnects in VLSI-based circuits”, SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , 17-20 Sept. 2003 Pages:243 — 244 [31] Seung Hoon Choi; Paul, B.C.; Roy, K.,” Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]”, Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings. , 7-11 Jan. 2002 Pages:65 - 70
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