臺灣博碩士論文加值系統

在本論文中提出一個採用I-Q錯誤校正技術且應用於IEEE 802.11a 5.2GHz 之CMOS射頻前端積體化接收器，其中只需使用控制電壓即可對於I-Q信號作立即矯正的動作，且易於應用於系統晶片上，另外此架構亦可針對不同相差之需求作設計或轉換，不需要依賴外接式被動元件，可提高性統之整合性。本論文規劃的接收器主要是以CMOS 0.18 um製程技術來實現，並透過國家晶片系統設計中心提供之製程完成，其中包含有單刀雙擲開關、低雜訊放大器、I-Q 調變器、偶次諧波混頻器、交互偶合式壓控震盪器等架構。本論文使用電路自動合成技術完成低雜訊放大器與壓控震盪器的之設計，且使用多閘級線性技術針對放大器線性度進行改善，此外針對一般單刀雙擲開關功率特性進行改善。本論文另外還針對模組電路部份進行設計與實作，並且嘗試在各元件與子電路中建立簡單的模型以準確完成接收器之整合與測試。
根據量測結果顯示，低雜訊放大器頻帶內之輸入輸出反回損耗都大於15dB、增益為8.2 、雜訊指數3.9dB、線性度之三接截斷點最佳可達到+2dBm的規格、正交射頻接收器則有大於20dB的輸入返回損耗、16.8dB的轉換增益、系統雜訊指數約10.67dB、三接截斷點-29dBm、相位雜訊 –118.9dBc/Hz@1MHz、輸出I-Q振幅錯誤與相位不平衡僅0.2dB與 、總功率消耗為134mW。

This thesis proposes a I-Q error correction technique for IEEE 802.11a 5.2GHz CMOS RF Front-End Receiver. This technique adopts voltage-controlled splitter to improve the I-Q mismatch immediately, the proposed topology is helpful for System On Chip (SOC) application. In addition, this topology can also provide the output of arbitrary phase difference. The off-chip passive components such as phase coupler or Balun is not required in this receiver, therefore it has more integrated and uncomplicated characteristics. This programmable receiver is realized in CMOS 0.18um process, and includes Single Pole Double Throw Switch(SPDT), Low Noise Amplifier(LNA), I-Q Modulator(I-QM), Even Harmonic Mixer(EHM), and Voltage Control Oscillator(VCO). A automatic circuit design method is used to design the LNA and VCO, a muti-gated transistors technique is adopted to improve the amplifier linearity and the power handing problem in SPDT switch is also solved. In module implementation, the simple model of each circuits and components has been developed in the combination of receiver module for testing precisely.
Measured results reveal that the low noise amplifier in design band has the input and output return loss of larger than 15dB, gain of 8.2 dB, and noise figure of 3.9 dB. The linearity achieves input third intercept point(IIP3) of +2dBm. The quadrature receiver possesses the input return loss of larger than 20dB, conversion gain of 16.8 dB, the noise figure of 10.67, IIP3 of -29dBm, phase noise of –118.9dBc /Hz @1MHz, the I-Q magnitude error and phase imbalance is 0.2 dB and respectively. Besides the power consumption is 134mW.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
附圖目錄 vi
表目錄 ix
第1章緒論.....1
1.1 發展現況.....1
1.2射頻前端系統架構與概念.....2
1.3 研究動機與接收器架構規劃.....13
1.4 論文架構.....18
第2章 5.2 GHz CMOS 低雜訊放大器與單刀雙擲開關.....20
2.1低雜訊放大器之設計..... 21
2.2高功率單刀雙擲開關之設計.....32
2.3晶片量測結果與討論..... 39
第3章 5.2 GHz I-Q 增益與相位調變器.....46
3.1 1-V 5.2 GHZ CMOS 多種相位功率校正器.....46
3.2 5.2 GHZ 增益控制器與雙級放大器設計..... 58
3.3量測結果與討論.....65
第4章 5.2 GHz CMOS偶次諧波降頻器與壓控震盪器之設計.....74
4.1 偶次諧波降頻器.....75
4.2交互耦合式電壓控制震盪器.....85
4.3晶片量測結果......92
第5章 5.2 GHz 直接降頻接收器之整合測試.....100
5.1 晶片線路設計考量.....100
5.2測試考量與設定.....102
5.3量測結果與討論.....104
第6章 結論與未來發展.....110
參考文獻 .....112
附錄A 改良式I-Q 增益調變器之量測結果..... 119
作者簡介.....122

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