臺灣博碩士論文加值系統

本論文設計2.4 GHz CMOS低電壓低雜訊放大器、降頻混頻器以及單晶片射頻接收機。在低電壓低雜訊放大器的設計上，利用折疊式的結構來達到低工作電壓的要求(小於1V)，經由量測增益在2.45 GHz為5.8 dB，輸入1dB增益壓縮點為-2.5 dBm，增益可調範圍為5.8 至-11.4 dB，雜訊指數為3.2 dB，功率消耗為7.2 mW。其次混頻器晶片也是採用TSMC 0.18 μm 1p6m 製程設計，量測增益在2.45GHz為5.28dB，輸入1dB增益壓縮點為-1dBm，輸出第三階截斷點為8.5 dBm。
第三，針對無線個人網路系統規範，進行單晶片射頻接收機之設計。其包含低雜訊放大器、混頻器、壓控增益放大器、低通濾波器及緩衝放大器。模擬結果為輸出振幅大於600mV，輸入1dB增益壓縮點為-17.5 dBm，整體消耗直流功率為12.7 mW。接收晶片中低雜訊放大器，在2.45 GHz的量測增益為16.1 dB，輸入1dB增益壓縮點為-13 dBm，雜訊指數為5.3 dB。

This thesis designs a 2.4 GHz CMOS sub-1-V low-noise amplifier, a down-converting micromixer, and a single-chip low-IF receiver. On the sub-1-V low noise amplifier, the folded-cascade configuration is employed to achieve the sub-one-voltage supply. The measured gain is maximal 5.8 dB with 17.2 dB tuning range. The noise figure is 3.2 dB and input P1dB is -2.5 dBm under 8mW DC power consumption. The micromixer is also designed with TSMC 0.18μm 1p6m process, where the measured conversion gain is 5.28 dB and input P1dB is -1 dBm. Finally, the single-chip CMOS receiver, adopting low-IF architecture, includes a low-noise amplifier, down mixer, IF variable gain amplifier, high-order low-pass filter and buffer amplifier, all implemented with TSMC 0.18μm process. The simulated baseband output voltage is 600 mV for driving the analog-to-digital converter under 12.7mW DC power consumption. The measured gain of LNA is 16.1 dB with 5.3 dB noise figure and -13 dBm input P1dB.

第一章 緒論 1
1.1 研究背景 1
1.2 無線個人網路概述 1
1.3 IEEE 802.15.4 (ZigBee) 7
1.4 研究目的及論文綱要 13
第二章 射頻接收架構分析 14
2.1 固定中頻超外差接收架構 14
2.2 正交超外差接收架構 18
2.3 直接降頻接收架構 19
2.4 低中頻接收架構 23
2.5 寬頻超外差接收架構 24
2.6 浮動中頻超外差接收架構 25
2.7 次取樣接收架構 26
2.8 數位中頻接收架構 ..27
2.9 射頻接收效能評估參數 ..28
第三章 低於1V 可調增益低雜訊放大器之設計與量測 38
3.1 簡介 38
3.2 CMOS電晶體雜訊指數模型 39
3.3 電晶體閘極寬度最佳化 41
3.4 低雜訊放大器種類介紹 43
3.5 低雜訊放大器設計流程 46
3.6 低於1-V可調增益低雜訊放大器 48
第四章 CMOS混頻器之設計與量測 57
4.1 簡介 57
4.2 混頻器原理 57
4.3 混頻器參數介紹及雜訊分析 61
4.4 2.4 GHz微混頻器 74
第五章 單晶片接收機之設計與量測 83
5.1 低雜訊放大器 83
5.2 降頻混頻器 93
5.3 壓控增益放大器與緩衝放大器 98
5.4 低通濾波器 104
5.5 接收機單晶片之模擬 105
5.6 接收機單晶片之量測 109
第六章 結論 114
參考文獻 115
附錄 115

[1]ANSI/IEEE Std 802.11, “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications,” 1999.
[2]IEEE Std 802.11a/D7.0, “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5 GHz Band,” 1999.
[3]IEEE Std 802.11b, “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-speed Physical Layer Extension in the 2.4 GHz Band,” 1999.
[4]IEEE P802.11g/D8.2, “Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Further Higher Data Rate Extension in the 2.4 GHz Band,” Apr. 2003.
[5]E. Callaway et al, “Home Networking with IEEE 802.15.4: A Developing Standard for Low-Rate Wireless Personal Area Networks,” IEEE Communications Magazine, pp. 69-77, Aug. 2002.
[6]J.A. Gutierrez et al, “IEEE 802.15.4: A Developing Standard for Low-Power Low-Cost Wireless Personal Area Networks,” IEEE Network Magazine, pp. 12-19, Sept. /Oct. 2001.
[7]S. Middleton, “IEEE 802.15 WPAN Low Rate Study Group PAR,” Document number IEEEP802.15-00/248r3, submitted Sep. 2000.
[8]I. Howitt and J. A. Gutierrez, IEEE 802.15.4 low rate-wireless personal area network coexistence issues, Wireless Communications and Networking (WCNC) , vol.3, pp. 1481-1486, 2003.
[9]B. Razavi, RF Microelectronics. Prentice Hall PTR, 1998.
[10]Web site: www.chipcom.com
[11]J. Crols and M. Steyaert, “Low-IF topologies for tigh-oerformance analog front ends of fully integrated receivers,” IEEE Transactions on Circuits and Systems, vol. 45, Mar. 1998.
[12]J. C. Rudell et. al., “A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications,” IEEE Journal of Solid-State Circuits, vol. 32, Dec. 1997.
[13]D. Sheng et. al., “A 900-MHz RF front-end with integrated discrete-time filtering,” IEEE Journal of Solid-State Circuits, vol. 31, Dec. 1996.
[14]A. Ong and B. Wooley, ”A two-path bandpass ΔΣ modulator for digital IF extraction at 20 MHz,” IEEE Journal of Solid-State Circuits, vol. 32, Dec. 1997.
[15]Application note 1314, “Testing and Troubleshooting Digital RF Communications Receiver Designs”, Agilent Technologies.
[16]張盛富，張嘉展，無線通訊射頻模組設計，全華書局，2005.
[17]T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998.
[18]D. K. shaeffer and T. H. Lee, “A 1.5-V, 1.5 GHz CMOS low-noise amplifiers,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 745-59, May 1997.
[19]T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applicatons” Proceedings of the 2003 Internationat Symposium , May. 2003.
[20]E. Sacchi, I. Bietti, F. Gatta, F. Svelto and R. Castello, “A 2dB NF, fully differential, variable gain, 900MHz CMOS LNA,” Symposium on VLSI Circuits Digest of Technical Papers, Jun, 2000.
[21]C. Y. Cha and S. G.. Lee, “A low power, high gain LNA topology,” Int. Microwave and Millimeter Wave Technology Conf. , pp. 420-423, 2000.
[22]C. Y. Cha and S. G.. Lee, “A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the Substrate Resistance,” IEEE J. of Solid-Stat Circuits, vol. 38, pp.669-672, Apr. 2003.
[23]A. A. Abidi, H.Darabi, “Noise in RF-CMOS Mixers: A Simple Physical Model”, IEEE Transactions on Solid State Circuits, vol. 35, no.1, pp. 15-25, Jan. 2000.
[24]R. G. Meyer et. al., “Noise in Current-Commutating CMOS Mixers”, IEEE Journal on Solid State Circuits, vol. 34, no.6, pp. 772-782, June. 1999.
[25]J. Durec, E.Main, “A Linear Class AB Single-Ended To Differential Transconverter Suitable for RF Circuits”, IEEE MTT-S Dig. , pp. 1071-1074 1996.
[26]C. C. Meng et. al., “A High Isolation CMFB Downconversion Micromixer Using 0.18-um Deep N-Well CMOS Technology”, IEEE Radio Frequency Integrated Circuits Symposium, pp. 619-622, 2003.
[27]Barrie Gilbert, “The Micromixer: A highly Linear Variant of The Gilbert Mixer Using A Bisymmetric Class AB Input Stage”, IEEE Journal of Solid State Circuits, vol. 32, no.9, pp. 1412-1423, Sept. 1997.
[28]K. L. Fong and R. G. Meyer “Monolithic RF Active Mixer Design,” IEEE Transactions on Circuits and Systems, vol. 46, pp. 231-239, Mar. 1999.
[29]C. Y. Cha, S.G. Lee, “A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance”, IEEE Journal of Solid State Circuits, vol. 38, no.5, pp. 669-672, Apr. 2003.
[30]T. K. K. Tsang and M. N. El-Gamal, “Gain controllable very low voltage ( 1 V) 8-9 GHz integrated CMOS LNAs” IEEE RFIC Symposium, Jun. 2002.
[31]S. A. Mass, Microwave Mixer, 2nd ed. Norwood, MA: Artech House, 1993.
[32]M. Mostafa and H. Elwan, “A 110 MHz 70 dB CMOS variable gain amplifier” IEEE international Symposium on Circuits and Systems, vol.2, pp.628-631, 30 May – 2 June 1999.
[33]V. Gopinathan, M. Tarsla and D. Choi, “A 2.5V, 30 MHz-100 MHz, 7th-order,equiripple group-delay continuous-time filter and variable gain amplifier implemented in 0.25um CMOS” IEEE International of Solid State Circuits Conference, pp. 394-395, 15-17 Feb. 1999.
[34]S. Sarkar, P. Sen, A. Raghavan, S. Chakarborty and J. Laskar, “Development of 2.4 GHz RF transceiver front-end chipset in 0.25 /spl mu/m CMOS,” in Proceedings of VLSI design 16th International Conference, pp. 42-47, 4-8 Jan. 2003.
[35]A. Karimi, H. Sjöland and A. Abidi, “A merged CMOS LNA and mixer for a WCDMA receiver,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1045-1050, Jun. 2001.
[36]M. Harada, T. Tsukahara and J. Yamada, “0.5–1-V 2-GHz RF front-end circuits in CMOS/SIMOX,” IEEE International Solid-State Circuits Conference, pp. 378-379., 2000
[37]D. R. Chambers, ”A Noise Source for Noise Figure Measurements,” Hewlett-Packard Journal, pp.26-27, April, 1983.
[38]Web site: www.agilent.com
[39]Web site: www.maxim-ic.com
[40]陶建安，無線個人網路之CMOS射頻發射晶片設計，國立中正大學電機工程研究所碩士論文，民國九十四年
[41]張凱貿，適用於WLNA和WCDMA雙模系統之射頻收發機系統模擬與CMOS低雜訊放大器設計，國立中正大學電機工程研究所碩士論文，民國九十三年
[42]T. K. K. Tsang and M. N. El-Gamal, “Gain and Frequency controllable SUB-1V 5.8 GHz CMOS LNA” ISCAS 2002, vol. 4, pp. 795-798, May. 2002.
[43]C. Y. Wang, S. S. Lu and C. C. Meng, “Wideband impedance matched GaInP/GaAs HBT Gilbert Micromixer with 12 dB Gain ” ASIC 2002, pp. 323-326, Aug. 2002
[44]C. C. Meng et. al., “A 5.2 GHz 16 dB Gain CMFB Gilbert Downconversion Mixer using 0.35μm Deep Trench Isolation SiGe BiCMOS Technology ” IEEE MTT-S Dig. , vol. 2, pp. 975-978, June 2004.
[45]T. K. K. Tsang and M. N. El-Gamal, “Gain and Frequency controllable SUB-1V 5.8 GHz CMOS LNA” ISCAS 2002, vol. 4, pp. 795-798, May. 2002