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研究生:徐膺傑
研究生(外文):Ying-Chieh Hsu
論文名稱:高效能低面積EBCOT-Tier-1編碼器
論文名稱(外文):High Performance and Low Cost EBCOT-Tier-1 encoder
指導教授:葉經緯
指導教授(外文):Ching-Wei Yeh
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:64
外文關鍵詞:EBCOTJPEG2000
相關次數:
  • 被引用被引用:0
  • 點閱點閱:242
  • 評分評分:
  • 下載下載:13
  • 收藏至我的研究室書目清單書目收藏:1
在本論文中,我們提出了一個高效能且低面積的EBCOT-tier-1 encoder,其包含兩個部分,1)Constant output rate CF、2)Input interleaving AE,其中constant output rate CF能以最少的時脈週期,處理完一個區塊。Input interleaving AE則為目前最快速的arithmetic encoder。相較於過去文獻提出的高效能EBCOT-tier-1 encoder,我們所提出的高效能EBCOT-tier1 encoder,因僅採用一組encoder,故在面積上較先前高效能的設計有大幅的縮減,且效能表現亦不差,當兩組各自獨立的CF操作在200Mhz,搭配一組input interleaving AE操作在400Mhz,時平均的效能可達74.4M samples/sec,可達HDTV 720p RGB(4:2:0)效能需求。
In this thesis, we propose an EBCOT-tier-1 encoder with high performance and low cost, which includes two parts: 1)Constant output rate CF, 2)Input interleaving AE. The constant-output rate CF can process a code block with the minimal number of clock cycles. The AE exploited the input-interleaving technique is the fast arithmetic encoder among all proposed literatures. Our proposed EBCOT-tier1 encoder employs one encoder so we can achieve much more area saving and maintain good performance in comparison with those encoders presented in related high performance works. 74.4M samples/sec can be realized by using two independent constant-output rate CFs operating at 200MHz and one input-interleaving AE operating at 400MHz. The sampling rate can be applied on the HDTV 720p RGB(4:2:0) application.
第一章 導論 2
1-1 簡介 2
1-2 動機 2
1-3 章節架構 3
第二章EBCOT-Tier-1 Encoder 演算法 4
2-1 EBCOT-Tier-1 Encoder 演算法 4
2-1.1 Context Formation (CF) 5
2-1.2 Arithmetic Encoder (AE) 10
2-2 相關設計 15
2-2.1 Context Formation(CF) 15
2-2.2 PASS Parallel 演算法 [17] 19
2-2.3 Arithmetic Encoder (AE) 22
2-2.4 AE Pipelining 23
第三章Proposed EBCOT-Tier-1 Encoder Architecture 25
3-1 Proposed Constant Output Rate CF 25
3-1.1 動機 25
3-2.2 Constant Output Rate CF 26
3-2 Proposed Input Interleaving AE 36
3-2.1 動機 36
3-2.2 Proposed Input Interleaving AE 38
3-3 Integration of CF and AE 42
3-3.1 Constant Output Rate CF搭配一般管線化AE 42
3-3.2 Constant Output Rate CF搭配Input Interleaving AE 44
第四章功能驗證與效能比較 48
4-1 功能驗證 49
4-2 實驗數據 53
4-3 數據比較 56
4-3.1 單一CF數據比較 56
4-3.2 EBCOT-Tier-1編碼器數據比較 57
4-3.3 EBCOT-Tier-1編碼器功率消耗探討 60
第五章 結論 61
[1] “JPEG 2000 Part I Final Committee Draft Version 1.0”, ISO/IEC JTC 1/SC 29/WG 1 N1646, March 2000.Available from http://www.jpeg.org

[2] David Taubman, “High Performance Scalable Image Compression with EBCOT”, IEEE Transaction on Image Processing, Vol. 9, No. 7, pp1158-1170, July 2000.

[3] David Taubman, Erik Ordentilich, Marcelo Weiberger, Gadiel Serouss, Ikuro Ueno and Fumitaka Ono, “Embedded Block Coding in JPEG2000”, Proceeding of the IEEE International Conference on Image Processing(ICIP), Vol. 2, pp 33-36, September 2000.

[4] Kuan-Fu Chen, Chung-Jr Lian, Hong-hui Chen and Liang-Gee Chen, “Analysis and Architecture Design of EBCOT for JPEG-2000”, IEEE International Symposium on Circuits and Systems, Vol. 2, pp 765-768, May 2001

[5] Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen and Liang-Gee Chen, “Analysis and Architecture Design of Lifting Base DWT and EBCOT for JPEG 2000”, Proceedings of Technical Papers of 2001 International Symposium on VLSI Tenchnology, System and Applications, pp180-183, April 2001.

[6] Yun-Tai Hisao, Hung-Der Lin, Kun-Bin Lee and Chein-Wei Jen, “High-Speed Memory-Saving Architecture for the Embedded Block Coding in JPEG2000”, IEEE International Symposium on Circuit and Systems, Vol. 5, pp 133-136, May 2002.

[7]Jen-Shiun Chiang, Yu-Sen Lin and Chang-Yo Hsieh, “Efficient Pass-Parallel Architecture for EBCOT in JPEG2000”, IEEE International Symposium on Circuits and System, Vol, pp773-776, May 2002.

[8] Kishore Andra, Chaitali Chakrabarti and Tinku Acharya, “A High Performance JPEG2000 Architecture”, IEEE International Symposium on Circuits and System, Vol 1, pp765-768, May 2002.
[9] Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen and Liang-Gee Chen, “Analysis and Architecture Design of Block-Coding Engine for EBCOT in JPEG2000”, IEEE Transactions on Circuits and Systems for Video Technology, Vol.13, No. 3,pp 219-230, March 2003.
[10]Kishore Andra, Chaitali Chakrabarti and Tinku Acharya, “A High Performance JPEG2000 Architecture”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 3, pp209-218, March 2003.

[11] Hung-Chi Fang, Tu-Chih Wang Chung-Jr Lian, Te-Hao Chang and Liang-Gee Chen , “High Speed Memory Efficient EBCOT Architecture for JPEG2000”, Proceeding of the 2003 International Symposium on Circuits and Systems, Vol. 2, pp 736-739, May 2003.

[12] Paul R. Schumacher, “An Efficient JPEG2000 Tier-1 Coder Hardware Implementation for Real-Time Video Processing”, IEEE Transactions on Consumer Electtonics, Vol. 49, No. 4, November 2003.

[13] Manjunath Gangadhar and Dinesh Bhatia, “FPGA based EBCOT Architecture for JPEG 2000”, Proceddings of the 2003 IEEE International Conference on Field-Programmable Technology(FPT), pp228-233, December 2003.

[14] Grzegorz Pastuszak, “ A novel architecture of arithmetic coder in JPEG2000 based on parallel symbol encoding”, Procedding of the 2004 IEEE International Conference on Parallel Computing in Electrical Engineering, pp303-308, September 2004.

[15] Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Tatsushi Ohyama, Yuh Matsuda, Tsugio Mori, Shin`ichiro Okada, Tsuyoshi Watanabe, Yoshihiro Matsuo, Yuji Yamada, Tatsuya Ichikwawa, Yoshifumi Matsuishita, “Image Processor Capable of Block-Noise-Free JPEG2000 Compression with 30frams/s for Digital Camera Applications”, ISSCC2003/SESSION2/MULTIMEDIA SIGNAL PROCESSING/PAPER2.5

[16] Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian, Liang-Gee Chen, “ 81MS/s JPEG2000 Signle-Chip Encoder with Rate-Distortion Optimization”, ISSCC2004/SESSION18/ CONSUMER SIGNAL PROCESSING/18.2.

[17]Hung-Chi Fang, Yu-Wei Chang, and Liang-Gee Chen, “ Area Efficient Architecture for the Embedded Block Coding in JPEG 2000”, The 47th IEEE International Midwest Symposium on Circuits and Systems.

[18] Leibo Liu, Ning Chen, Hongying Meng, Li Zhang, Zhihua Wang, and Hongyi Chen, “ A VLSI Architecture of JPEG2000 Encoder”, IEEE Journal OF Soild-Sstate Circuit(JSSC), vol. 39, NO. 11, November 2004.

[19] Hideki Yamauchi, Shigeyuki Okada, Kazuhiko Taketa, Yuh Matsuda, Tsugio Mori, Tsuyoshi Watanabe, Yoshihiro Matsuo, and Yoshifumi Matushita, ”1440 x 1080 Pixel, 30 Frames Per Second Motion-JPEG 2000 Codec for HD-Movie Transmission”, IEEE Journal of Solid-State Circuits(JSSC), vol.40, NO. 1, January 2005.

[20]Oscal T.-C. Chen, Robin Ruey-Bin Sheen,”A Power-Efficient Wide-Range Phase-Locked Loop”, IEEE Journal of Solid-State Circuits, Vol. 37, NO. 1, January 2002
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