臺灣博碩士論文加值系統

隨著晶片所能容納的元件越來越多，因為本身的溝通架構(communication
architecture)所消耗掉的(工力)率;已經佔了整體所能消耗的(工力)率裡相當大的比率。在晶
片系統裡有著各式各樣不同的組成元件，而他們在(工力)能及溝通的需求上都不相
同，所以，設計一個溝通拓撲(communication topology)時，就應該針對這些元件
不同的溝通情況以及工作負載來做最佳化的調整設計。在本篇論文裡，我提出一
個創新的連結架構，這個架構可以利用十字型轉換開關動態的建構出兩個元件中
一個專屬的溝通路徑。我將會介紹針對不同的應用，根據profile的一些溝通特
徵，如何去建構出匯流排溝通架構的設計策略。根據應用的溝通情況，我設計了
兩種匯流排操作模式。第一種模式屬於動態執行仲裁(arbitration)的模式，這就是
一般當各個元件組合到匯流排上時，十字型轉換開關將會根據每個元件所發出的
request加以判斷，並決定由哪一個元件得以傳輸資料。第二種模式則是預先決定
十字型轉換開關所開啟的方向(路徑)，透過這種預先決定的方式，固定了十字型
轉換開關裡仲裁的動作，也就是說，不需再經過仲裁的動作，藉此省下執行仲裁
動作所消耗的(工力)率;。我使用MPEG4 decoder和JPEG的工作負載來做實驗，而實驗
結果顯示出，如果我們可以知道嵌入式軟體的應用，我們將可以善加控制十字型
轉換開關以及產生適當的匯流排的架構以得到較佳的效能及較低的(工力)率消耗。

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should optimally match communication workflows among these components. In this paper, we first propose a novel interconnect
architecture, which uses crossroad switches to dynamically construct a dedicated communication path between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design two application-specific bus operation schemes. The first scheme is dynamically-controlled arbitration, where a core placement tool automatically
maps the cores to communication topologies such that the bus is shared and controlled at run time and the total communication energy can be minimized. The second scheme is the pre-determined control assignment for switches. Each switch may operate in a ”lease line” mode, which can dynamically offer a dedicated path between two high-communicative cores for a specific period according to the application characteristics. We take the MPEG4 decoder
and JPEG as our case studies, and experimental results show the power consumptions can be saved if we organize cores carefully and dynamically control NoC switches when the behavior of the embedded software is well-known.

1 Introduction 1
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Background and Related Work 7
2.1 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Crossroad Bus Architecture 18
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 The Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Segmenting a bus for power optimization . . . . . . . . . . . . . . . . . . . . 21
3.4 Bus Control and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 Self-routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2 Analysis of delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.1 Fully Configurable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.2 Power Optimization by Localization . . . . . . . . . . . . . . . . . . . 33
3.5.3 Better Communication Parallelism . . . . . . . . . . . . . . . . . . . 33
4 Strategies on Crossroad Bus Architecture 35
4.1 Tailoring Crossroad Bus Architecture to Application-Specific SoC . . . . . . 35
4.2 Dynamic Switch Mode Assignment for Temporary Lease Path . . . . . . . . 37
4.2.1 Pre-determined Mode of the Switch . . . . . . . . . . . . . . . . . . . 37
4.2.2 Mode Selection for Each Switch . . . . . . . . . . . . . . . . . . . . . 39
5 Experiment and Performance Evaluation ................................42
5.1 Evaluation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 Evaluation Results of Bus Architectures . . . . . . . . . . . . . . . . . . . . 45
5.3 Effects of Placement Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.4 Effects of the Bus Configurable Controller and Pre-determined Mode Selection ................................................................54
6 Conclusion and Future Work 61

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