(3.230.76.48) 您好!臺灣時間:2021/04/11 09:49
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:簡國安
研究生(外文):Guo-An Jian
論文名稱:應用於MPEG-4音訊編碼及音訊殘響之可重組及參數化硬體加速矽智財
論文名稱(外文):A Reconfigurable and Parameterized Hardware Accelerating IP for MPEG-4 Audio Coding and Reverberation
指導教授:郭峻因
指導教授(外文):Jiun-In Guo
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:56
中文關鍵詞:矽智財參數化離散傅立葉轉換反向改良式離散餘弦轉換音訊殘響
外文關鍵詞:ReverberationIMDCTParameterizedIPDFT
相關次數:
  • 被引用被引用:0
  • 點閱點閱:153
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:27
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要包含可重組之參數化離散傅立葉轉換(DFT)及反向改良式離散餘弦轉換(IMDCT)硬體架構實作及矽智財設計,透過電路架構的共享,FFT、IFFT及IMDCT可以在同一硬體架構上實現,避免浪費不必要的硬體資源,在電路弁鄐W,本文所提的設計可提供MPEG-4 AAC解碼所需的256點及2048點IMDCT運算,在此同時,也針對音訊殘響(Reverberation)提供1024點FFT及IFFT運算加速。另一方面,為了讓電路設計更具彈性,我們提供一些參數讓使用者根據其需求調整硬體架構,相信在面對各式各樣SoC應用的系統需求時,這樣的特性將有益於電路的設計與發展。
This thesis presents an IP design and implementation of a reconfigurable and parameterized hardware circuit for discrete Fourier transform (DFT) and inverse modified discrete cosine transform (IMDCT). Through circuit sharing, FFT, IFFT, and IMDCT are carried out with the same hardware architecture. This strategy can prevent from wasting unnecessary hardware resources. It supports 256-point and 2048-point IMDCT for MPEG-4 AAC decoding as well as 1024-point FFT and IFFT for audio reverberation. Considering high flexibility, this IP provides some parameters for users to adjust the hardware architecture according to their needs. Such a feature is helpful and beneficial especially for satisfying system requirements of different SoC (System on Chip) applications.
摘要 i
Abstract ii
Acknowledgments iii
Contents iv
List of Illustrations vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Scope of The Thesis 3
Chapter 2 Previous Works 4
2.1 FFT 4
2.1.1 Butterfly Method 4
2.1.2 Multi-path Delay Method 7
2.1.3 Single-path Delay Method 9
2.2 IMDCT 11
2.2.1 SISO Approach 12
2.2.2 PIPO Approach 13
2.3 Reverberation 14
2.3.1 Reverberation 14
2.3.2 FIR-based Approach 16
2.3.3 IIR-based Approach 18
Chapter 3 Proposed Design 21
3.1 Proposed Algorithm 21
3.2 Proposed Architecture 23
3.2.1 Memory-based Processing Unit 23
3.2.2 Coefficient ROM 25
3.2.3 Control System 30
Chapter 4 Design Verification and IP Realization 34
4.1 Design Verification 34
4.1.1 Behavioral Verification 34
4.1.2 RTL Verification 35
4.1.3 Formality Verification 36
4.1.4 Gate-level Verification 36
4.2 IP Generator Design 36
4.3 IP Verification 38
Chapter 5 Simulation and Performance Analysis 40
5.1 Precision Analysis 40
5.2 Synthesis Results 41
Chapter 6 Conclusion and Future Work 43
6.1 Conclusion 43
6.2 Future Work 44
References 45
[1]ISO/IEC 11172-3, “Coding of moving picture and associated audio for digital storage media at up to about 1.5Mbit/s — Part 3 audio”, November 1991.
[2]ISO/IEC 13818-7, “Information Technology - Generic Coding of Moving Pictures and Associated Audio, Part 7: Advanced Audio Coding”,1997.
[3]ISO/IEC JTC1 SC29/WG11, “ISO/IEC FDIS 14496-3 Subparts 1, 2, 3, Coding of Audio-Visual Objects - Part 3: Audio, ”October 1998.
[4]J. C. McKinney, R. Hopkins, “Digital Audio Compression Standard (AC-3)”, Advanced Television Systems Committee, Revision A/52, 20, December 1995.
[5]James W. Cooley and John W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Math. Comput. 19, 297–301 (1965).
[6]L. R. Rabiner and B. Gold, “Theory and Application of Digital Signal Processing”, Prentice-Hall, 1975.
[7]E. H. Wold and A. M. Despain, “Pipeline and Parallel-pipeline FFT Processors for VLSI Implementation”, IEEE Trans. Computers, C-33 (5), pp.414-426, 1984.
[8]L. Jia, Y. Gao, J. Isoaho and H. Tenhunen, “A new VLSI-oriented FFT algorithm and implementation”, Proc. IEEE ASIC Conference, pp. 337-341, 1998.
[9]Y. T. Lin, P. Y. Tsai, T. D. Chiueh, “A Low-Power Variable-Length Fast Fourier Transform Processor VLSI”, Proc. IEEE ISPACS, 2002.
[10]J. Princen and A. Bradley. "Analysis/Synthesis Filter Bank Design Based on Time Domain Aliasing Cancellation", IEEE Transactions, ASSP-34, No. 5. Oct. 1986. pp. 1153-1161.
[11]H. C. Chiang and J. C. Liu, “Regressive implementation for the forward and inverse MDCT in MPEG audio coding,” IEEE Signal Processing Lett., vol. 3, pp. 116–118, Apr. 1996.
[12]V. Britanak and K. R. Rao, “An Efficient Implementation of the Forward and Inverse MDCT in MPEG Audio Coding”, IEEE Signal Processing Lett., vol. 8, pp. 48-51, Feb. 2001.
[13]Yun-Hui Fan, V. K. Madisetti, and R. M. Mersereau, “On fast algorithms for computing the inverse modified discrete cosine transform”, IEEE Signal Processing Letters, Volume 6, Issue 3, March 1999, pp. 61-64.
[14]Szu-Wei Lee, “Improved Algorithm for Efficient Computation of the Forward and Backward MDCT in MPEG Audio Coder”, IEEE Transactions on Analog and Digital Signal Processing, Volume 48, Issue 10, Pages: 990 – 994, Oct. 2001.
[15]W. G. Gardner, “Efficient Convolution without Input-Output Delay”, J. Audio Eng. Soc., vol. 43, no. 3, pp. 127-136, March 1995.
[16]K. Iida, K. Mizushima, Y. Takagi, and T. Suguta, “A New Method of Generating Artificial Reverberant Sound”, 99th AES Convention 1995 October 6-9, 1995.
[17]A. V. Oppenheim and R. W. Schafer, “Discrete-Time Signal Processing”, Prentice-Hall, Englewood Cliffs, NJ, 1989.
[18]M. R. Schroeder and B. F. Logan, “Colorless Artificial Reverberation”, J. Audio Eng. Soc., vol. 9, no. 3, pp. 192-197, July 1961.
[19]M. R. Schroeder, “Natural Sounding Artificial Reverberation”, J. Audio Eng. Soc., vol. 10, no. 3, pp. 219-223, July 1962.
[20]J. A. Moorer, “About This Reverberation Business”, Computer Music Journal, vol. 3, no. 2, pp. 13-28, June 1979.
[21]J. M. Jot and A. Chaigne, “Digital delay networks for designing artificial reverberators”, in Proc. 90th Conv. Audio Eng. Soc., February, 1991, preprint 3030.
[22]J. Dattorro, “Effect Design Part 1: Reverberator and Other Filters”, J. Audio Eng. Soc., vol. 45, pp. 660-684, September 1997.
[23]P. Duhamel, Y. Mahieux, J. P. Petit, ”A fast algorithm for the implementation of filter banks based on time domain aliasing cancellation”, Proc. IEEE ICASSP, Toronto, Canada, pp. 2209-2212, 1991.
[24]Ching-Hsien Chang, Chin-Liang Wang, and Yu-Tai Chang, “A novel memory-based FFT processor for DMT/OFDM applications”, Acoustics, Speech, and Signal Processing, 1999. Proceedings. 1999 IEEE International Conference on, Volume: 4, pp. 1921-1924, 1999.
[25]Chin-Liang Wang and Ching-Hsien Chang, “A DHT-based FFT-IFFT processor for VDSL transceivers”, Acoustics, Speech, and Signal Processing, 2001. Proceedings. 2001 IEEE International Conference on, Volume: 2, pp. 1213-1216, 2001.
[26]C.-H. Chang, C.-L. Wang, and Y.-T. Chang, "Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse", IEEE Trans. Signal Processing. vol. 48, pp. 3206-3216, NOV. 2000.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔