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研究生:張修誠
研究生(外文):Hsiu-Cheng Chang
論文名稱:應用於MPEG-4AVC/H.264視訊編碼標準之低成本高效能通曉內容可變長度解碼器IP設計
論文名稱(外文):A Novel Low-Cost High-Performance VLSI Architecture for MPEG-4 AVC/H.264 AVLC Decoding
指導教授:郭峻因
指導教授(外文):Jiun-In Guo
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:40
中文關鍵詞:CAVLCH.264HDTVlow-power design
外文關鍵詞:CAVLCH.264HDTVlow-power design
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近年來,對於視訊畫質的需求越來越高,也因此在壓縮方面需要更好的效率,在MPEG-4 AVC/H.264 使用了CAVLC取代傳統的VLC設計來增加壓縮效率,可以展現更好的效能。本篇論文提出了應用於MPEG-4 AVC/H.264視訊編碼標準之低成本高效能通曉內容可變長度解碼器的數位超大型積體電路架構設計,論及到五個特殊的技術來降地硬體成本及達到低必v的效果,甚至是增加資料流,他們分別是PCCF (Partial combinational component Freezing), HLLT (Hierarchical logic for Look-up tables), ZTEBA (Zero-left table elimination by arithmetic), IDS (Interleaved Double Stacks)和ZCS (Zero Codeword Skip)。另外,為了確保IP設計之正確性,分別在不同的層次進行個別模擬和系統之驗證,其中包含了RTL驗證、Gate層級驗證以及Chip實作。本設計,在125MHz的工作頻率和0.18μm CMOS製程設計下,它的硬體成本是4720 gates,而且效能上足以滿足HD1080i影像規格即時播放。最後,晶片實作結果證明,我們所提出的低必v設計,比原先沒加上低必v的設計,減少了百分之五十五的必v消耗。
The demand of high quality video and high data compression enables the MPEG-4 AVC/H.264 adopting the Context-based Adaptive Variable Length Code (CAVLC) technique as contrary to the traditional MPEG-4 VLC techniques. This paper presents a novel low-cost, high-performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC decoding. In the proposed design, we exploit five different techniques to reduce both the hardware cost and power consumption, as well as increase the data throughput rate. They are PCCF (Partial combinational component Freezing), HLLT (Hierarchical logic for Look-up tables), ZTEBA (Zero-left table elimination by arithmetic), IDS (Interleaved Double Stacks), and ZCS (Zero Codeword Skip). As a result, the proposed design can decode every syntax element per cycle. The synthesis result shows that the design achieves the maximum speed at 175 MHz. When we synthesize the proposed design at clock constraint of 125MHz, the hardware cost is about 4720 gates under a 0.18μm CMOS technology, which achieves the real-time processing requirement for H.264 video decoding on HD1080i format video@30Hz. Moreover, the proposed low power design techniques reduce the power consumption of the proposed design up to 55 % as compared to the original one.
Chapter 1: Introduction 4
Chapter 2 : Previous Works 7
Chapter 3 : Proposed Algorithm for CAVLD 11
3.1 CAVLD Decoding Flow 11
3-2: Optimized flow for CAVLD 13
Chapter 4 : Architecture Design and System Integration 16
4.1 Architecture for CAVLC decoder 16
4.2 Architecture for Coeff_Token decoder 18
4.3 Architecture for T1 decoder 19
4.4 Architecture for Level decoder 19
4.5 Architecture for TotalZero decoder 20
4.6 Architecture for Run_Before decoder 21
4.7 IDS (Interleave Double Stacks) buffering 22
4.8 IDS (Interleave Double Stacks) Operating Flow 23
4.9 System Integration 25
Chapter 5 : IP Realization 28
5.1 IP Design Flow 28
5.2 IP Verification Stategy: 29
5.2 IP Qualification: 30
Chapter 6: Performance and Comparison 33
Chapter 7 : Conclusion 37
References 38
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