跳到主要內容

臺灣博碩士論文加值系統

(100.26.196.222) 您好!臺灣時間:2024/03/02 22:27
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:曾志豪
研究生(外文):Chih-Hao Tseng
論文名稱:針對動態可重組式計算系統之基於統一塑模語言的快速開發流程
論文名稱(外文):UML-Based Rapid Prototyping Design Flow for Dynamically Reconfigurable Computing Systems
指導教授:熊博安熊博安引用關係
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:65
中文關鍵詞:統一塑模語言循序圖開發流程可重組式計算系統動態可重組式
外文關鍵詞:UMLSequence DiagramDesign FlowReconfigurable ComputingDynamic Reconfiguration
相關次數:
  • 被引用被引用:1
  • 點閱點閱:269
  • 評分評分:
  • 下載下載:28
  • 收藏至我的研究室書目清單書目收藏:0
動態可重組式計算系統提供了在計算系統設計上,可同時具有效能與彈性的設計考量,然而設計動態可重組式計算系統具有相當高的複雜度,而且是一項艱鉅的工作,雖然在學術界與業界有釵h的研究正在進行中,但是缺乏工具與設計流程的輔助使得設計師不願採用可重組式計算技術。本論文提出了一個針對動態可重組式計算系統之基於統一塑模語言的設計流程,此流程著重在藉由動態可重組式計算系統來加速應用程式中演算法的執行,並且可減少設計動態可重組式計算系統時那些複雜與耗時的工作。在所提出的設計流程中,特別值得一提的特色是一個基於統一塑模語言第二版中循序圖的軟硬體分割方法論,簡稱為DBPSD,DBPSD中包含了軟硬體分割的指導方針,用來輔助設計師在類別的方法層級上作出精明的分割決策,在統一塑模語言第二版中加強語法的循序圖,具有了描述複雜控制流程的能力,因此可以在循序圖上作有效率的軟硬體分割。為了證明所提出之設計流程與軟硬體分割方法論的可行性,本論文實作了一個DES加解密系統的實例,從實作的結果可以發現應用程式中不同的控制流程影響了每一個方法被呼叫的次數,因此證明了在循序圖上根據控制流程作軟硬體分割的重要性與價值。
Dynamically reconfigurable computing systems (DRCS) provides an intermediate tradeoff between flexibility and performance of computing systems design. Unfortunately, designing DRCS have a high complexity and is a formidable task. Although many researches are ongoing in the academia and industry, but the lack of tools and design flows discourage designers from adopting the reconfigurable computing technology. A UML-based design flow for DRCS is proposed in this Thesis. The proposed design flow is targeted at the execution speedup of functional algorithms in DRCS and at the reduction of the complexity and time-consuming efforts in designing DRCS. In particular, the most notable feature of the proposed design flow is a HW-SW partitioning methodology based on the UML 2.0 sequence diagram, called Dynamic Bitstream Partitioning on Sequence Diagram (DBPSD). Besides, partitioning guidelines are also included in DBPSD to help designers make prudent partitioning decisions at the class method granularity. The enhanced sequence diagram in UML 2.0 is capable of modeling complex control flows, thus the partitioning can be done efficiently on the sequence diagrams. To prove the feasibility of the proposed design flow and DBPSD partitioning methodology, an implementation example of DES (Data Encryption Standard) encryption/decryption system is presented in this Thesis. It was found from the implementation result that different control flows affect the number of times each method is invoked in an application. Thus, the worth of doing partitioning on sequence diagram according to control flow is proved.
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Proposed Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Previous Work 8
3 The Design Flow 12
3.1 Design and Implementation of System Software Model . . . . . . . . . . . . . . 14
3.2 Hardware Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 20
3.3 Software Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 23
3.4 Target Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 The HW/SW Partitioning on Sequence Diagrams 29
4.1 The Partitioning Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 The DBPSD Partitioning Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Application Examples 35
5.1 Example 1: SW Multiplier VS. HW Multiplier . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Example 2: Reconfiguration between HW Multiplier and HW Adder . . . . . 41
5.3 Example 3: SW CRC-16 Generator VS. HW CRC-16 Generator . . . . . . 42
5.4 Example 4: A DES Instant Message Security System . . . . . . . . . . . . . . . . 43
6 Conclusions 46
Bibliography 47
[1] Rhapsody case tool reference manual. I-Logix Inc. http://www.ilogix.com.
[2] T. Beierlein, D. Frӧhlich, and B. Steinbach. UML-based co-design for run-time reconfigurable architectures. In Proc. of the Forum on Specification and Design Languages (FDL’03), pages 5–19, September 2003.
[3] T. Beierlein, D. Frӧhlich, and B. Steinbach. Model-driven compilation of UML-models for reconfigurable architectures. In Proc. of the Second RTAS Workshop on Model-Driven Embedded Systems (MoDES’04), May 2004.
[4] K. Bondalapati and V. K. Prasanna. Reconfigurable computing systems. Proceedings of the IEEE, 90(7):1201–1217, July 2002.
[5] G. Booch, J. Rumbaugh, and I. Jacobson. Unified Modeling Language User Guide. Addison-Wesley, 1999.
[6] T. J. Callahan and J. Wawrzynek. Instruction-level parallelism for reconfigurable computing. In Proc. of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, pages 248–257. Springer-Verlag, Berlin, August 1998.
[7] K. Compton and S. Hauck. Reconfigurable computing: A survey of systems and software. ACM Computing Surveys, 34(2):171–210, June 2002.
[8] J. Fleischmann, K. Buchenrieder, and R. Kress. A hardware/software prototyping environment for dynamically reconfigurable embedded systems. In Proc. of the 6th International Workshop on Hardware/software Codesign, pages 105–109. IEEE Computer Society, March 1998.
[9] J. Fleischmann, K. Buchenrieder, and R. Kress. Java driven codesign and prototyping of networked embedded systems. In Proc. of the 36th ACM/IEEE Design Automation Conference (DAC’99), pages 794–797. ACM Press, June 1999.
[10] S. Kimura, M. Yukishita, Y. Itou, A. Nagoya, M. Hirao, and K.Watanabe. A hardware/software codesign method for a general purpose reconfigurable co-processor. In Proc. of the 5th International Workshop on Hardware/Software Co-design (CODES/CASHE’97), pages 147–151. IEEE Computer Society, March 1997.
[11] Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood. Hardware-software co-design of embedded reconfigurable architectures. In Proc. of the 37th ACM/IEEE Design Automation Conference (DAC’00), pages 507–512. IEEE Computer Society, June 2000.
[12] N. Narasimhan, V. Srinivasan, M. Vootukuru, J. Walrath, S. Govindarajan, and R. Vemuri. Rapid prototyping of reconfigurable coprocessors. In Proc. of the International Conference on Application Specific Systems, Architectures, and Processors (ASAP), pages 303–312. IEEE Press, August 1996.
[13] K. D. Nguyen, Z. Sun, P. S. Thiagarajan, and W. F. Wong. Model-driven SoC design via executable UML to SystemC. In Proc. of the 25th IEEE International Real-Time Systems Symposium (RTSS’04), pages 459–468. IEEE Computer Society, December 2004.
[14] I. A. Niaz and J. Tanaka. Mapping UML statecharts to Java code. In Proc. of the IASTED International Conference on Software Engineering (SE 2004), pages 111–116, February 2004.
[15] J. Noguera and R. M. Badia. HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4):399–415, August 2002.
[16] A. Pelkonen, K. Masselos, and M. Cupak. System-level modeling of dynamically reconfigurable hardware with SystemC. In Proc. of the 10th Reconfigurable Architectures Workshop (RAW’03), 17th International Symposium on Parallel and Distributed Processing (IPDPS’03), pages 174–181. IEEE Computer Society, April 2003.
[17] I. Robertson and J. Irvine. A design flow for partially reconfigurable hardware. ACM Transactions on Embedded Computing Systems, 3(2):257–283, May 2004.
[18] F. Vahid and T Givargis. Embedded System Design: A Unified Hardware/Software Introduction. John Wiley & Sons, 2002.
[19] Q. Zhu, A. Matsuda, S. Kuwamura, T. Nakata, and M. Shoji. An object-oriented design process for system-on-chip using UML. In Proc. of the 15th International Symposium on System Synthesis (ISSS’02), pages 249–254. ACM Press, October 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top