臺灣博碩士論文加值系統

在高效能的處理器中乘法器佔有最長的運算時間及大量的使用次數，所以對乘法器而言，低必v及高速度的要求變得十分重要，且因多媒體運算的需求，乘法器常需支援多重資料流的模式，也就是SIMD（Single Instruction Multi Data），本論文即針對SIMD乘法器的各種需求，提出了釵h項新穎的設計，並整合成IC下線。Post layout simulation數據顯示，我們的設計，速度較所參考的文獻快了約30%，繞線面積減少約22%，必v消耗最多可以改善約30%。

Among high performance processors, it is multiplier which needs the longer operation time and which is used with high frequency. Therefore, for multiplier， low power and high speed are of importance. Also, due to the needs of the multi-media operation, multiplier needs Single Instruction Multi Data mode, that is, SIMD mode. This essay aims at providing many novel designs to meet the various needs of SIMD multiplier, and these designs are integrated into IC type-out. According to Post layout simulation, compared with those references it shows that my design is faster in speed about 30%, is less in routed area about 22, and is lower in power dissipation about 30%.

第一章
1-1研究動機
1-2論文章節安排
第二章
2-1相關研究發展現況
2-2疊接結構SIMD乘法器 (Bottom Up SIMD Multiplier)
2-3陣列式SIMD乘法器【2】
2-3.1陣列式結構的無號運算
2-3.2陣列式結構的有號無號運算
2-3.3 陣列式乘法器支援2組無號SIMD運算
2-3.4 陣列式乘法器支援4組或2組有號無號SIMD運算
2-4 Shared Subtree SIMD乘法器
2-4.1部份乘積產生
2-4.2 Partial Product Reduction Tree
2-5 結合Modified Booth與Wallace tree之SIMD乘法器【3】
2-5.1 支援SIMD的Modified Booth Multiplier
2-5.2 Booth Encoder因應無號數的修正
2-5.3 Booth selector（Booth Decoder）因應無號數的修正
2-5.4 符號延伸與內部清除為零
2-5.5 SIMD Multiplier內部必須清除的Carry-out
2-5.6 Carry kill Final adder
第三章
3-1 SIMD乘法器簡介 3
3-2 考量硬體內部之面積及速度設計法
3-2.1 High-Speed Modified Booth
3-3 SIMD multiplier之硬體共用改造
3-3.1 切割乘數使Booth運算支援SIMD
3-3.2 支援無號數所增加的Booth Encoder硬體化簡
3-3.3支援無號數所增加的Booth Decoder(Booth Selector)
3-3.4支援SIMD運算的符號延伸
3-3.5 Signed Generate內部邏輯共用的實現
3-3.6 內部反向加一之解決
3-3.7 支援SIMD切換內部必須清除為零
3-3.8支援SIMD切換內部加法器Carry-out必須清除為零
3-3.9 總整理
3-4 Modified Booth搭配陣列結構加法器(Carry-save addition)
3-4.1 Modified Booth搭配陣列結構在必v消耗的改良
3-5 Modified Booth搭配Wallace tree 架構
第四章
4-1 效能比較與分析
4-2 Verilog 設計與驗證
4-3 Synopsys軟體合成數據分析
4-4 Pre-Sim Timing 數據分析
4-4.1 Pre-sim 波型驗證
4-5 繞線後的面積比較
4-6 Post- layout simulation Timing
4-7 Post layout simulation速度分析比較
4-8 Post layout Simulation 必v消耗分析
4-8.1 我們的設計與reference design的必v消耗分析
4-8.2 Post-Sim Power Report without Wallace tree
4-8.3 Modified Booth演算法搭配上陣列結構加法必v消耗分析
4-9 Post-Simulaition Transistor Count report
第五章
參考文獻
附 錄
1.SIMD multiplier 下線接腳規劃
2.下線接腳圖
3.PIN assignment

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