臺灣博碩士論文加值系統

此論文設計三個應用於RGB影像處理之低必v八位元高速管線式類比/數位轉換器：第一個設計採用傳統式每級1.5位元之架構，其內部需要7個放大器與15個比較器，量測結果在2 MS/s下，輸入訊號為9.8 kHz可得到SNDR為33.45 dB、ENOB為5.26位元。為了降低必v消耗，第二個設計採用放大器共用技術，可使運算放大器數目降低為4個。而在第三個設計中，本文提出之放大器與比較器共用技術僅需4個放大器與9個比較器，可進一步降低系統的必v消耗。其中OPAMP架構採用全差動的方式設計，並使用tsmc 0.35um 2P4M Mixed Signal Process實現，在操作電壓為3.3伏、140 MS/s下，當輸入訊號為9.34 MHz時, 由post-layout simulation結果可得到訊號雜訊失真比為44.02 dB、有效位元為7.02 Bit、微分非線性度介於+0.45/-0.5 LSB、積分非線性度介於+2.33/-0.36 LSB、總必v消耗為118.1 mW，與傳統式架構相比可降低約33%的必v消耗。

Three architectures of 8-Bit high speed pipelined A/D Converters for RGB image processing is implemented. Firstly, a conventional 1.5-bit/stage pipelined ADC required 7 amplifiers and 15 comparators is designed and fabricated. According to measured results, the SNDR of 33.45 dB under sampling frequency of 2 MHz and input signal of 9.8 kHz is obtained. The ENOB is 5.26 Bit. In order to reduce the power comsumption, the amplifier sharing technique with only 4 amplifiers is included in the 1.5-bit/stage pipelined ADC design. Finally, with only 4 amplifiers and 9 comparators is proposed in the third 1.5-bit/stage pipelined ADC design to further reduce the power consumption. For the OPAMP implementation, the fully differential structure is used. The ADC is implemented in tsmc 0.35um 2P4M Mixed Signal Process thchnology, Based on the post-layout simulation, the ADC SNDR and ENOB are 44.02 dB and 7.02 Bit, respectively, with an input frequency of 9.34 MHz under sampling frequency of 140 MHz. The DNL is about +0.45/-0.5 LSB, and INL is about +2.33/-0.36 LSB. The total ADC power consumption under supply voltage of 3.3 V is about 118.1 mW. The technique will achieve a power saving of 33% compared with conventional pipelined ADC.

中文摘要 I
ABSTRACT II
誌謝 III
目錄 V
圖目錄 VIII
表目錄 XI

第1章 緒論 1
1.1 研究動機 1
1.2 論文概述 2
第2章 高速類比/數位轉換器架構 3
2.1 類比/數位轉換器特性參數 3
2.2 快閃式(FLASH)類比/數位轉換器架構 9
2.3 二階式(TWO-STEP)類比/數位轉換器架構 10
2.4 多階管線式(MULTI-STAGE PIPELINED)類比/數位轉換器架構 11
2.5 類比/數位轉換器總結 14
第3章 1.5-BIT/STAGE管線式類比/數位換器 15
3.1 設計原理 15
3.2 管線式類比/數位轉換器行為模型 19
第4章 電路設計 24
4.1 管線式類比/數位轉換器設計需求 24
4.1.1 運算放大器增益與穩定時間 24
4.1.2 放大器的線性度 26
4.1.3 MOS開關 27
4.1.4 取樣電容 33
4.1.5 運算放大器的負載電容 34
4.1.6 JITTER的影響 35
4.2 運算放大器 37
4.2.1 MOSFET輸出阻抗 37
4.2.2 MOSFET轉換頻率 38
4.2.3 運算放大器架構 39
4.2.4 寬織T偏壓電路 44
4.2.5 共模回授電路 45
4.3 取樣保持電路 46
4.4 SUB-ADC 48
4.4.1 動態比較器 48
4.4.2 1.5-BIT/STAGE SUB-ADC 50
4.4.3 2-BIT FLASH ADC 51
4.5 MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (MDAC) 52
4.6 時脈產生器 54
4.7 移位暫存器與數位錯誤修正電路 56
4.8 模擬結果 59
4.9 效能總結 61
第5章 放大器與SUB-ADC共用之ADC設計 62
5.1 原理 62
5.2 電路設計 63
5.2.1 放大器共用技術之MDAC 63
5.2.2 SUB-ADC共用技 66
5.3 電路佈局 68
5.4 模擬結果 70
5.5 效能總結 74
5.6 類比/數位轉換器評量標準 76
第6章 量測步驟與實驗結果 77
6.1 量測環境 77
6.2 量測結果 80
第7章 結論 85
參考文獻 86

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