臺灣博碩士論文加值系統

本論文提出在多媒體電路的資料路徑上，探討與減少轉態必v消耗問題。並提出低必v演算的電路設計，稱為仰制虛必v消耗技術(SPST)。仰制虛必v消耗技術的概念是把運算單元切分成高位元部份與低位元部份，每當高位元部份在不影響運算結果下，減少高位元部份的轉態發生，並且消除高位元電路的轉態存在，有效地減少必v消耗。在本論文中探討幾種實現仰制虛必v技術設計的作法，並選擇最有效能的設計，最後應用在MPEG-4 AVC/H.264的轉換編碼設計上。
SPST應用於H.264轉換架構[39]，當操作在電壓1.8伏且執行頻率 22MHz / 50 MHz /100MHz 的高效能多重轉換設計，在使用SPST弁鄐U，佈局後實驗可以節省約為27.4% /27.4%/ 27.3%的必v消耗，從中指出在H.264的多重轉換編碼設計上，SPST能有效地減少必v消耗，有助於視訊編碼應用於可攜式電子元件上。

This thesis presents the design exploration and application of a technique to suppress the spurious power dissipation existed in the data-paths for multimedia designs. The proposed designs are arithmetic circuits of low power technique, also named Spurious Power Suppression Technique (SPST). It adopts the design concept of separating the arithmetic units into Most Significant Part (MSP) and Least Significant Part (LSP), and then freezing the MSP whenever this part of circuits does no affect the computation result. The proposed technique eliminates the glitch switches exited in them to effectively decrease the power dissipation. This technique explores several implementation approaches of realizing the SPST-based design concept to decide the most efficient one, and then its applications on an MPEG-4 AVC/H.264 transform coding design.
H.264 transform design [39] uses this approach to reduce the switching power. The post-layout simulation results show that turning on the SPST function can save 27.48%/27.37%/27.28% power dissipations respectively when the SPST-based ETD is operated at 22MHz/50MHz/100MHz with 1.8V supply voltage. This indicates that the proposed SPST technique can effectively reduce the power dissipation in the transform coding designs for H.264, which facilitates video coding applications on portable electrical devices.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖列 vi
表列 viii
第1章 序論 1
1-1 引言 1
1-2 研究方向 3
1-3 論文章節概述 3
第2章 低必v演算電路設計 4
2-1 研究動機 4
2-2 相關研究發展 6
2-3 低必v演算電路架構 8
2-3.1 電路架構 8
2-3.2 偵測電路單元(Detection Logic unit, DL) 8
2-3.3 資料進出控制器單元(Data In-Out Control unit, DIOC) 10
2-3.4 符號延伸補償單元(Sign Extension unit, SE) 11
2-4 實驗數據 12
2-4.1 資料進出控制器單元與符號補償單元不同邏輯閘比較 12
2-4.2 實驗結論 13
2-4.3 相關研究比較 14
第3章 多媒體電路應用 16
3-1 簡介視訊壓縮編碼 16
3-2 多重轉換編碼 17
3-2.1 4×4轉換編碼運算演算法 17
3-2.2 4×4多重轉換編碼電路架構 18
3-2.3 分析轉換編碼輸入範圍 21
3-2.4 必v分析 22
第4章 高效率低必v二維多重轉換編碼 24
4-1 相關研究發展 24
4-2 研究動機 28
4-3 直接二維轉換演算法 29
4-4 高效能二維多重轉換編碼 31
4-5 高平行度二維多重轉換編碼 32
4-6 系統整合設計考量 33
4-7 效能综合比較 36
4-7.1 電路架構必v比較 36
4-7.2 综合比較 40
4-7.3 相關研究數據比較 43
第5章 矽智產實現 44
5-1 簡介矽智產 44
5-2 矽智產設計流程 45
5-3 弁鉬P架構 46
5-4 相關特性 47
5-5 參數化內容 49
5-6 驗證及量測環境 50
5-6.1 設計模組 50
5-6.2 驗證策略 52
5-6.3 晶片量測 55
5-6.4 設計自動化執行檔 56
5-7 應用方法及實例 56
5-7.1 圖形介面產生器 56
5-7.2 具體之應用實例 59
第6章 晶片設計 60
6-1 晶片設計觀念 60
6-2 晶片架構設計 61
6-3 測試考量 62
6-4 實驗模擬 66
6-4.1 佈局前模擬 66
6-4.2 佈局後模擬 67
6-5 佈局平面圖與晶片規格 68
第7章 結論與未來展望 69
参考文獻 70
成果發表 74

[1] Yu-Wen Huang, Bing-Yu Hsieh, Tu-Chih Wang, Shao-Yi Chien, Shyh-Yih Ma, Chun-Fu Shen, and Liang-Gee Chen, “Analysis and Reduction of Reference Frames for Motion Estimation in MPEG-4 AVC/JVT/H.264,” Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2003 vol.03, pp. 145-148, April 2003.
[2] A.P. Chandrkasan, R. W. Brodersen, ”Minimizing power consumption in digital CMOS circuits,” Proc. Of the IEEE, vol: 83, No. 4, pp. 495-523, April 1995.
[3] Junghwan Choi; Jinhwan Jeon; Kiyoung Choi; “Power minimization of functional units by partially guarded computation” Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on 2000 Page (s):131 - 136
[4] Chen, O.T.-C.; Sheen, R.R.-B.; Wang, S.;“A low-power adder operating on effective dynamic data ranges” IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 10, Issue 4, Aug. 2002 Page(s):435 - 453
[5] L. Liu, Q. Lin, M. Rong, and J. Li, “A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture,” Proceedings of the 4th IWSOC, Pages: 158- 161, 19-21 July 2004.
[6] R. Kordasiewicz, and S. Shirani, “Hardware implementation of the optimized transform and quantization blocks of H.264,” IEEE CCECE, Pages: 943-946, Vol.2, 2-5 May 2004.
[7] I. Amer, W. Badawy, and G. Jullien, “Hardware prototyping for the H.264 4x4 transforms,” IEEE ICASSP, Pages: V - 77-80, vol.5, 17-21 May 2004.
[8] Z.-Y. Cheng, ea. al., “High throughput 2-D transform architectures for H.264 advanced video coders,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 1141-1144, Dec. 6-9, 2004.
[9] I. Richardson, “H.264/MPEG-4 part 10: Transform and Quantization,” December, 2002, available on http://www.vcodex.fsnet.co.uk/h264_transform.pdf.
[10] Jordi Ribas-Corbera, Philip A. Chou, and Shankar L. Regunathan, “A Generalized Hypothetical Reference Decoder for H.264/AVC,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 674-687, July 2003.
[11] Swee-Yeow Yap and John V. McCanny, “A VLSI Architecture for Advanced Video Coding Motion Estimation,” Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 293-301, June 2003.
[12] Peter List, Anthony Joch, Jani Lainema, Gisle Bjøntegaard, and Marta Karczewicz, “Adaptive Deblocking Filter,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 614-619, July 2003.
[13] Yu-Wen Huang, Bing-Yu Hsieh, Tu-Chih Wang, Shao-Yi Chien, Shyh-Yih Ma, Chun-Fu Shen, and Liang-Gee Chen, “Analysis and Reduction of Reference Frames for Motion Estimation in MPEG-4 AVC/JVT/H.264,” Proc. IEEE International Conference on Multimedia and Expo, ICME 2003 vol.02, pp. 809-812, July 2003.
[14] Yu-Wen Huang, To-Wei Chen, Bing-Yu Hsieh, Tu-Chih Wang, Te-Hao Chang, and Liang-Gee Chen, “Architecture Design for Deblocking Filter in H.264/JVT/AVC,” Proc. IEEE International Conference on Multimedia and Expo, ICME 2003, vol.01, pp. 693 - 696, July 2003.
[15] Detlev Marpe, Heiko Schwarz, and Thomas Wiegand, “Context-based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 620-636, July 2003.
[16] Markus Flierl and Bernd Girod, “Generalized B Pictures and the Draft H.264/AVC Video-compression Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 587- 597, July 2003.
[17] Michael Horowitz, Anthony Joch, Faouzi Kossentini, and Antti Hallapuro, “H.264/AVC Baseline Profile Decoder Complexity Analysis,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 704 -716, July 2003.
[18] Thomas Stockhammer, Miska M. Hannuksela, and Thomas Wiegand, “H.264/AVC in Wireless Environments,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 657 -673, July 2003.
[19] Stephan Wenger, “H.264/AVC Over IP,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 645 -656, July 2003.
[20] Yu-Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen, “Hardware Architecture Design for Variable Block Size Motion Estimation in MPEG-4 AVC/JVT/ ITU-T H.264,” Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2003 vol. 2, pp. 796-799, May 2003.
[21] Wing-Cheong Chan; Oscar, C. Au; Ming-Fai Fu, “Improved Global Motion Estimation Using Prediction and Early Termination,” Proc. IEEE International Conference on Image Processing 2002, vol. 2, pp. 285-288, Sept 2002.
[22] K. Denolf, C. Blanch, G. Lafruit, and J. Bormans, “Initial Memory Complexity Analysis of the AVC CODEC,” Proc. IEEE Workshop on Signal Processing Systems, SIPS 2002, pp. 222-227, Oct 2002.
[23] Ajay Luthra, Gary J. Sullivan, Thomas Wiegand, “Introduction to the Special Issue on the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 557 -559, July 2003.
[24] Thomas Wiegand, Gary J. Sullivan, Gisle Bjøntegaard, and Ajay Luthra, “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 560-576, July 2003.
[25] Siwei Ma, Wen Gao, Peng Gao, and Yan Lu, “Rate Control for Advance Video Coding (AVC) Standard”, Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2003 vol. 2, pp. 892-895, May 2003.
[26] Marta Karczewicz and Ragip Kurceren, “The SP- and SI-Frames Design for H.264/AVC,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 637-644,
[27] R. Schafer, T. Wiegand and H. Schwarz, “The emerging H.264/AVC standard,” EBU TECHNIQUE REVIEW, January, 2003, available on http://www.ebu.ch/trev_293-schaefer.pdf.
[28] H. Malvar, A. Hallapuro, M. Karczewicz, and L. Kerofsky, “Low-Complexity Transform and Quantization in H.264/AVC,” IEEE Transaction on Circuit and System for Video Technology, vol. 13, No. 7, pp.598-603, July, 2003.
[29] T. Wang, Y. Huang, H. Fang, and L. Chen, “Parallel 4x4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264,” Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2003, pp. 800-803, 2003.
[30] L. Liu, Q. Lin, M. Rong, and J. Li, “A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture,” Proceedings of the 4th IWSOC, Pages: 158 -161, 19-21 July 2004.
[31] R. Kordasiewicz, and S. Shirani, “Hardware implementation of the optimized transform and quantization blocks of H.264,” IEEE CCECE, Pages: 943-946, Vol.2, 2-5 May 2004.
[32] I. Amer, W. Badawy, and G. Jullien, “Hardware prototyping for the H.264 4x4 transforms,” IEEE ICASSP, Pages: V - 77-80, vol.5, 17-21 May 2004.
[33] Z.-Y. Cheng, ea. al., “High throughput 2-D transform architectures for H.264 advanced video coders,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 1141-1144, Dec. 6-9, 2004.
[34] J. Korris, and M. Macedonia, “The end of celluloid: digital cinema emerges,” Computer, vol. 35, issue 4, pp. 96-98, March 2002.
[35] H. Iwasaki, et. al., “Single-chip MPEG-2 422p@HL CODEC LSI with multi -chip configuration for large scale processing beyond HDTV level,” Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE’03), pp. 2-7, 2003.
[36] M. Ghanbari, “Video coding-an introduction to standard CODECs” The institution of electrical engineers, 1999.
[37] M. Keating and P. Bricaud, “Reuse Methodology Manual for system-on-a-chip designs,” third edition, Kluwer academic publishers.
[38] Artisan component, “TSMC 0.18 mm process 1.8-volt SAGE-X standard cell library Databook,” September 2003.
[39] Kuan-Hung Chen, Jiun-In Guo and Jinn-Shyan Wang, “Efficient Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264”Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s) :4517 - 4520