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研究生:賴羿臣
研究生(外文):I-Chen Lai
論文名稱:使用GALS架構之FFTButterfly設計
論文名稱(外文):The Design of a GALS-Based FFT Butterfly
指導教授:陳仁德陳仁德引用關係
指導教授(外文):Ren-Der Chen
學位類別:碩士
校院名稱:長庚大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:93
語文別:中文
外文關鍵詞:GALS、asynchronous、extended-burst-mode、metastability
相關次數:
  • 被引用被引用:0
  • 點閱點閱:230
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  • 下載下載:28
  • 收藏至我的研究室書目清單書目收藏:0
在本論文中,我們設計一個非同步介面模組來實現整體非同步局部同步(Globally Asynchronous Locally Synchronous, GALS)電路。我們將每個同步電路周圍加入非同步介面模組來達成我們的設計,該非同步介面模組是由局部時脈產生器以及輸入/輸出控制器來組成,並且可以經由一般EDA工具來設計合成。最後,我們設計一個FFT Butterfly電路來驗證我們的方法。
In this paper, we propose an asynchronous wrapper for GALS(Globally Asynchronous Locally Synchronous) circuit. Synchronous circuits are equipped with asynchronous wrappers in our design, these wrappers are assembled from locally clock generater and input/output controls which synthesized by EDA tools. Finally, we design a FFT Butterfly circuit to examine our methodology。
中文摘要 iii
英文摘要 iv
目錄 v
圖目錄 viii
表目錄 x
第一章 緒論 1
第二章 非同步技術的介紹 3
2.1 非同步資料轉移 3
2.2 交握式協定 4
2.2.1 二相位協定 4
2.2.2 四相位協定 5
2.3 Hard-free circuit 5
2.4 Extended-burst-mode 7
2.5 Extended-burst-mode合成工具 8
2.6 Metastabillty 9
2.7 Globally Asynchronous Locally Synchronous 10
第三章 非同步介面模組 11
3.1 非同步資料轉移 12
3.2 預防metastability的辦法 14
3.3 局部時脈產生器 14
3.4 輸出控制器 16
3.5 輸入控制器 17
第四章 FFT Butterfly 20
4.1 演算法 20
4.2 同步管線式FFT Butterfly架構 23
4.2.1 IEEE 754 浮點數標準 25
4.2.2 加法器/減法器電路 25
4.2.3 乘法器電路 26
4.3 GALS架構之FFT Butterfly 27
第五章 實驗結果 29
5.1 設計流程與工具 29
5.1.1 Design Analyzer工具 31
5.1.2 Debussy工具 32
5.1.3 Prime Power工具 32
5.1.4 Silicon Ensemble工具 32
5.2 GALS架構之FFT Butterfly行為模擬 33
5.3 GALS架構之FFT Butterfly電路合成 38
5.3.1 D-FF、加法器/減法器與乘法器時間分析 38
5.3.2 GALS架構之FFT Butterfly Postsynthesis模擬 40
5.3.3 GALS架構之FFT Butterfly postsynthesis面積與功率分析 42
5.3.4 GALS架構之FFT Butterfly back-annotation模擬與APR 44
5.4 同步管線式之電路合成 46
5.4.1 同步管線式FFT Butterfly Postsynthesis模擬 46
5.4.2 同步管線式FFT Butterfly postsynthesis面積與功率分析 48
5.5 FFT Butterfly back-annotation功率分析 49
5.6 同步管線式FFT Butterfly與GALS架構之FFT Butterfly分析 50
第六章 結論 51
參考文獻 52
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