本電路架構主要是以一notch filter將位於800MHz處的影像濾除,以最基本的疊接組態與源極電感退化式匹配網路為主; 疊接組態能使整個架構的增益提高, 源極電感退化式匹配網路可使輸入阻抗匹配至50歐姆,而且其NF低, 有助於LNA的設計. 本低雜訊放大器主要的功能是在於其消除影像的能力, 並將一般匹配網路用的電感”擠”在同一個晶片上以減少外加打線所造成的誤差,且盡量地縮小晶片面積, 使的整個晶片面積在1.1mm乘以1.1mm之內. 整個系統操作在2.4GHz的頻率之下, 供應電壓為1.8V, 其中低雜訊放大器的偏壓電流為5.98mA, 功率消耗為10.764mW, 雜訊指數2.355dB, 增益15.6dB, S11與S22皆小於-15, 影像拒斥能力有32.392dB, P1dB為-23, IIP3為-9.846, 而其穩定度皆大於1. 本論文所設計的電路在模擬方面用的是安捷倫的ADS軟體, 電路佈局使用Cadence, 晶片的實現是採用國家晶片中心CIC所提供的台灣積體電路有限公司的0.18um 1P6M CMOS製程.

Proposed circuit used a notch filter to eliminate the image at 800MHz and adopted a basic cascade structure combined with inductor degeneration terminal as matching network. Cascade structure makes gain arise and inductor degeneration terminal as 50 ohms of input matching. Its low NF also helps the design of LNA. The proposed image-rejection low noise amplifier’s main function is giving the image-reject ability while “squeeze” the inductors for matching networks on the same chip in order to depress the loss of bond wire. Then reduce the chip as possible and the whole die area is under 1.1mmx1.1mm. The whole system is operated in the frequency of 2.4GHz and the supply voltage of 1.8V. The proposed Image-Reject Low Noise Amplifier here is biased by the current of 5.98mA, power consumption of 10.764mW, Noise Figure of 2.355dB, gain of 15.6dB, S11 and S22 are smaller than -15, the image-reject ability is 32.392dB, P1dB of -23, IIP3 of -9.846 and the stability are more than 1. The circuit presented in this thesis was been simulated with Agilent ADS and layout with Cadence. The implementation of chip adopted the TSMC 0.18um 1P6M CMOS process which provided by National Chip Implementation Center.

指導教授推薦書………………………………………..…………………
口試委員會審定書………………………………………..………………
Abstract (In Chinese)…………………………………………………... I
Abstract (In English)……………………………………...…..…………II
Acknowledgement………………………...………………………….…III
Contents………………………...…………………...………………..…IV
Table Captions……………………………………….………………….VI
Figure Captions…………………………………….………………...…VI


CHAPTER 1 INTRODUCTION
1.1 Background…………………………………….…………….………1
1.2 Thesis Organization……………………………….…………………3

CHAPTER 2 RECEIVER SYSTEM and ARCHITECTURE
2.1 Introduction…………………………………..………………………4
2.2 Superheterodyne Receiver………….………………...………………4
2.3 Direct-Conversion Receiver………………………...………………..6
2.3.1 Drawbacks of Direct-Conversion Receiver…………………….7
2.4 Low-IF Receiver…………………………………………………….10
2.5 Unreasonable Characteristics of Transceiver……………………......11
2.5.1 Noise..…………………………………………………………11
2.5.2 The Noise from Transistor Inside………….……………...…12
2.5.3 Channel Thermal Noise………….………………………..…13
2.5.4 Distributed Gate Resistance Noise………………………..….14
2.6 Characteristics of A Receiver……………………..……………...…15
2.6.1 Noise Figure…..………………………………………………15
2.6.2 Intermodulation Distortion……………………………………17
2.6.3 IP3…………………………………………………………..…18
2.6.4 1dB Compression Point……..………………………………...19

CHAPTER 3 1.8V 2.4G IMAGE-REJECTION LNA
3.1 Resonant Circuits………………..…………………………………..20
3.2 Series Resonant…………………..…………..……………………...20
3.3 Parallel Resonant………………..…………………………………..21
3.4 Image Distortion of A Superheterodyne Receiver…………………..24
3.5 High IF………………………………………………………………25
3.6 Low IF………….…………………….……………………………..26
3.7 Matching Architectures………….…………………………………..27
3.8 Proposed Image-Rejection LNA………..…………………………..35
3.9 Design Flow Path……………………………………………………41
3.10 Simulation Results…………………………………………………42
3.11 Conclusion…………………………………………………………45

CHAPTER 4 MEASUREMENT CONSIDERATION
4.1 Estimative Specification…….…..…………………………………..51
4.2 Chip Measurement……….……………………..…………………..52

CHAPTER 5 FUTURE PROSPECT OF CMOS
5.1 Future Prospect………..………………………………..…………54

REFERENCES………..…………………………………….………56

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