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研究生:許惠欣
研究生(外文):Hui-Hsin Hsu
論文名稱:利用射頻濺鍍對氧化釓閘極絕緣層的特性研究
論文名稱(外文):Characteristics of Gd2O3 Gate Dielectric Deposited by Reactive RF-sputterin
指導教授:賴朝松
指導教授(外文):Chao-Sung Lai
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:44
中文關鍵詞:氧化釓
外文關鍵詞:gadolinium oxideHysteresis
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依據ITRS,隨著金氧半場效電晶體(MOSFET)的尺寸不斷進行微縮,如通道長度和閘極氧化層二氧化矽厚度持續縮小,將面臨到許多嚴重的瓶頸;當氧化層厚度小於30nm時,其明顯的閘極直接穿透漏電流的增加和硼穿透效應會產生,繼而引起高功率消耗,嚴重影響元件特性;為了解決和改善此問題,新的絕緣層材料成為現今熱門的研究方向,如Ta2O5,Al2O3,HfO2,Gd2O3等等。但這些材料還有一些難以克服的問題存在,才無法完全取而代之,如熱穩定性和遲滯現象(Hysteresis),高介面電荷等,材料本身也會在sputtering因高溫下容易與矽表面形成一層Interfacial Layer(IL); 在本篇論文裡,其目的在對新穎的稀土族元素高介電層材料氧化釓(Gd2O3)用RF濺鍍方式來沉積後,再經高溫熱退火研究其電性和遲滯(Hysteresis)現象的探討;我們可以發現Gd2O3經過高溫製程後,原本較鬆散結構層會再重新組成而表現更致密,其崩潰電壓會隨溫度升高而明顯增加,EOT亦是隨溫度上升而下降;此外,這材料的電容特性並不會隨著頻率升高而有所下降,在溫度的影響下讓氧化層陷補電荷(Qot)會發生轉態。
According to the ITRS (International Technology Roadmap for Semiconductor), the dimension of devices were scaling down focus on the channel and gate silicon dioxide thickness to be decreased decrease rapidly. It would face several problems. As the oxide thickness less than 3nm, the gate leakage current and boron penetration through oxide are more seriously to influence the properties of devices. In order to resolve these questions, that the replacement of SiO2 was required by High-k dielectric materials and I researched extensively, such as Ta2O5, Al2O3, HfO2, Gd2O3 ..etc. However, the thermal stability in contact with Si is a challenge for high-k gate dielectrics due to the crystallization during the thermal processes. The formation of interfacial layer and silicides would depend on the deposition conditions.
In this thesis, I figured out that the first time gadolinium dioxide was deposited on Si substrate by RF-sputtering then investigated the properties and hysteresis phenomenon with rapid thermal annealing. We found this thin film exhibits excellent electrical properties such as improved hysteresis phenomenon, frequency dispersion and a higher breakdown voltage. In addition, the decrease of the EOT under high-temperature annealing is due to the densification of gadolinium dioxide film, making the dielectric film more stoichiometric.
Contents
Chapter 1 Introduction
1-1 CMOS Technology Scaling Trends……………………….1
1-2 Gate oxide scaling trends and limiting factors……………1
1-3 Improve device performance from High-k gate dielectric..3
1-4 The motivation in this study ……………………………...4

Chapter 2 The Characteristics of Gadolinium Oxide Films on
Silicon Substrate by RF-sputtering
2-1 Introduction ..……………………………………………...6
2-2 Experiment ………………………………………………..9
2-3 Result and Discussion …………………………………….13
2-4 Summaries ………………………………………………...16


Chapter 3 The Hysteresis phenomenon of Gadolinium Oxide Films
3-1 Introduction ……………………………………………….24
3-2 Experiment ………………………………………………..29
3-3 Result and Discussion …………………………………….33
3-4 Summaries ………………………………………………...35


Chapter 4

Conclusion ………………………………………………………41


Reference ……………………………………………………42
Reference
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