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研究生:翁臺謙
研究生(外文):Tai-Chien Weng
論文名稱:直接序列展頻通訊系統之低功率類比相關器
論文名稱(外文):The Low Power Analog Correlator for Direct Sequence Spread Spectrum Communications
指導教授:馮武雄馮武雄引用關係
指導教授(外文):Wu-Shiung Feng
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:66
中文關鍵詞:直接序列展頻類比相關器
外文關鍵詞:Direct Sequence Spread Spectrumanalog correlator
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本論文為實現一個應用在,直接序列展頻通訊系統中的低功率類比相關器。在相關器中,可以使用數位電路方式和類比電路方式來實現,但如果跟其前端的類比對數位轉換器( ADC )加以考量後,數位電路加類比對數位轉換器的功率消耗,將比類比電路來的高,因此採用了類比電路來完成相關器電路。
低功率的類比相關器電路,可採用被動式電路,和主動式電路,而在此選擇被動式電路來完成相關器電路,其優點有:不需要主動式電路中的運算放大器,而減少了運算放大器的功率損耗,也不用受到放大器的迴轉率的穏定時間而限制了操作頻率,所以被動式相關器符合了低功率的消耗。最後使用UMC 0.18µm 1P6M CMOS製程,經模擬後,實現一個操作頻率為16MS/s,功率消耗為0.5mW的類比相關器。
This thesis presents the development of low power analog correlator for direct sequence spread spectrum communications. The correlation would be implemented in the digital and analog architectures. Considered frond-end analog to digital converter ( ADC ), in digital architecture, the ADC must have high speed sampling rates and high power consumption. To avoid the power consumption of a high-speed ADC, decision to select the analog architecture.
For implementing an analog correlator can use active correlation or passive correlation. To select passive correlation, it includes the following advantages: no integrating capacitor is needed. The combination of all the sampling capacitors forms the integrating capacitor, no opamp is needed. Switches perform the charge transfer, no settling time restriction by an opamp’s bandwidth, no opamp power dissipation.
With considerations the lowest power consumption, this architecture is the most suitable choice for the analog correlator. The simulation results of analog correlator to achieve a 0.5mW power dissipation and a 16MS/s processing rate with UMC 0.18µm standard CMOS technology.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x

第一章 導論 1
1.1 簡介 1
1.2 研究動機 2
1.3 論文架構 3

第二章 展頻系統架構 4
2.1 簡介 4
2.2 直接序列展頻 5
2.3 跳頻展頻 8
2.4 假隨機碼原理與架構 10
2.5 假隨機碼之特性 12

第三章 類比相關器原理與架構 15
3.1 簡介 15
3.2 採樣開關 17
3.2.1 MOS 開關 17
3.2.2 MOS 開關電荷誤差改善方法 20
3.3 類比相關器架構 25
3.3.1 主動式相關器 26
3.3.2 被動式相關器 28
3.4 元件匹配考量 35
3.5 雜訊考量 38

第四章 類比相關器電路模擬 39
4.1 假隨機碼產生器 39
4.2 相關器取樣單元電路 41
4.3 時序產生器 46
4.4 位移暫存器電路 53
4.5 相關器電路模擬結果 55
4.6 佈局及量測考量 59
4.7 規格列表 62

第五章 結論與未來展望 63
5.1 結論 63
5.2 未來展望 63

參考文獻 64
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