近年來，電腦已成為我們日常生活中不可或缺的物品，然記憶體又是電腦相當重要的零件，由於製程的日新月異，使得記憶體容量不斷攀升，目前個人電腦中記憶體容量，動輒512MB，甚至1GB比比皆是，因此要修補記憶體也就變成相當冗長。前人已提出許多找尋記憶體修補解的方法，雖可達到修補的目的，所花時間仍相當長，因此才有RUD快速篩選的程式。然此判斷流程中仍有不少地方未盡仔細，有許多部分仍無法判讀是否有解。故本論文針對此RUD的流程再做部分修改，並將RUD無法判讀的部分利用其他方法來補強，使得在求解及執行速度上能夠更為快速。

Computer has become requisite in recent years; however, the memory is one of the important elements. With the progression of semiconductor process, the memory capacity is increasing rapidly, even with 1GB recently. Large memory requires long time to test. Many methods had been proposed to search repair solutions. They cost long time, therefore need the help of fast algorithms. The previous algorithm, i.e. RUD, has some questions e.g. cannot deal with many faulty maps.
This thesis focuses on improving RUD with proposed new methods. Experimental results show that the mew methods can repair memory rapidly and correctly.

第一章 簡介.....................................1
1.1 研究動機.................................1
1.2 研究內容.................................2
1.3 章節概要.................................2
1.4 預備.....................................3
第二章 各種記憶體修復方式.......................4
2.1 FLCA.....................................4
2.2 兩方向有效係數法.........................8
2.3 FCECA....................................11
2.4 判斷記憶體不可修復及可修復之策略.........14
第三章 ARUD判斷策略............................21
3.1 ARUD策略簡介............................21
3.2 RUD待改進地方...........................24
3.3 ARUD策略................................26
3.3.1 ARUD的LE選取法......................26
3.3.2 適當redundant line選擇..............30
3.3.3 處理Sno..............................34
3.4 ARUD程序流程............................36
第四章 實驗及討論...............................38
4.1 實驗配備.................................38
4.2 實驗設定條件及目的.......................38
4.3 結果及討論...............................39
第五章 結論.....................................41

參考資料
[1].R. C. Evans, ”Testing repairable RAMs and mostly good memories”, in Proc. 1981 IEEE Int. Test Conf, pp. 49-55.
[2].B. Tarr, D. Boundreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories”, Electronics, pp. 175-179, Jan. 12. 1984.
[3].J. R. Day, “A fault-driven comprehensive redundancy algorithm”, IEEE Design and Test, pp. 35-44, June 1985.
[4].F. Lombardi and W. K. Huang, “Approaches for the repair of VLSI/WSI RRAMs by row/column deletion”, in Proc. 18th Int. Conf. Fault-Tolerant Comput. Symp. (FTCS-18), July 1988, pp. 342-347.
[5].S-Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays”, in Proc. 1986 ACM/IEEE Design Automat. Conf. Pp. 385-390. Also in IEEE Design and Test, vol. 4, no. 1, pp 24-31, Feb. 1987.
[6].N. Hasan and C. L. Liu, ”Minimum fault coverage in reconfigurable arrays”, in Proc. 18th Int. Conf. Fault-Tolerant Comput. Symp. (FTCS-18), July 1988, pp. 348-353.
[7].C-L. Wey and F. Lombardi, “On the Repair of Redundant RAMS”, IEEE Trans. on CAD of ICAS, Vol. CAD 6, No. 2, pp.222-231, 1987.
[8].何文清（民91），記憶體修補之多餘行列選擇法。長庚大學半導體科技研究所碩士論文。
[9].鄭明杰（民92），記憶體可修復性及不可修復性之判斷策略。長庚大學半導體科技研究所碩士論文。