臺灣博碩士論文加值系統

現代積體電路工業的趨勢是閘極通道長度將不斷的減少，當通道長度小於某一個程度時，元件的短通道效應及反轉短通道效應所造成臨界電壓及飽和電流的偏移就越顯重要。本論文中，我們提出將碳離子植入DRAM 記憶體cell transistor汲極端的應用技術。在DRAM cell 電晶體的製程中有許多道的離子植入製程,例如: well、源極和汲極、源極和汲極halo、表面臨界電壓調整、接觸窗植入等等。從DRAM 記憶體的製程結構，源極和汲極端的halo植入是為抑制源極和汲極端穿隧效應。由於源極和汲極halo植入而造成DRAM cell元件的反轉短通道現象，而這種現象將會造成元件的臨界電壓上升及飽和電流的下降。換句話來說就是DRAM記憶體元件的效能下降，所以它會容易造成整個 DRAM cell bit的讀寫失敗或讀寫速度的下降。我們應用碳離子植入 DRAM cell 電晶體的汲極端，並且它可以改善這些問題。我們可以從一些資料得知，碳離子植入cell transistor 的汲極端可以抑制源極和汲極halo的硼離子擴散現象。所以在本論文中，我們將利用電性測試的方式來討論應用碳離子植入矽晶圓的一些電性效應，這包含了元件的臨界電壓、次臨界漏電、飽和電流、元件roll-off效應、閘極引發汲極的漏電及接面的漏電，並評估不同劑量的碳離子對元件的效應。我們也可以從 chip probe (CP) 良率測試的結果來獲得碳離子的植入可以改善提昇DRAM記憶體的良率，而良率的改善包含了資料保持及資料的讀寫，所以可從實驗中得知碳離子的植入確實能呈現良好的電性效應。

The decrease of gate channel length is a trend in modern ULSI in-dustry. As the gate channel length become smaller, short channel effect (SCE) and reverse short channel effect (RSCE) of DRAM cell transistor will cause the shift of threshold voltage (Vt) and the degradation of satu-rated drain current (Idsat). In this thesis, we have proposed carbon im-plantation into drain for application of DRAM cell transistor technology. There are many implantation processes in DRAM cell transistor. For example: well, source/drain, halo, surface voltage adjusting and contact implantation. Based on DRAM cell device structure, drain side has halo boron-fluoride (BF2) implantation to prevent punch-through. Due to drain halo implant, RSCE is caused on DRAM cell transistor. RSCE will lead to high threshold voltage (Vt) and low saturated drain current (Idsat) is. In other words, RSCE will also bring about MOSFET's performance degra-dation, and will easily lead to the failure of write-back failure easily. We have used carbon implantation into the drain of cell transistor to improve those issues. Different carbon dosage implanted into the drain of cell transistor will be discussed in this thesis and will investigate the impact of carbon dopant on the electrical properties of cell transistor. Boron diffu-sion, activation, and critical electrical parameters including threshold voltage (Vt), saturated drain current (Idsat), subthreshold swing (S.S), threshold voltage roll-off, gate-drain overlay capacitance (Cgd), gate in-duced drain leakage (GIDL) and junction leakage have been evaluated as a function of the carbon dosage from wafer electrical testing (WET) in-formation. Based on chip probe (CP) testing results, carbon implant can improve CP yield and it includes both data retention and short-write-back (SWB).

Abstracts....................................................vi

Chapter 1
Introduction................................................... 1
1.1 Background................................................. 1
1.2 Classical Methodology of Electrical Measurement............ 2
1.3 Electrical Test Methodology of DRAM Cell Transistor........ 3
1.4 Test Element Group (TEG) of Electrical Measurement......... 5

Chapter 2
A Introduction of DRAM Cell Transistor Process Flow........... 15
2.1 Introduction.............................................. 15
2.2 Active area (AA) of DRAM Cell Transistor Process Flow..... 16
2.3 Gate conductor (GC) of DRAM Cell Transistor Process Flow.. 17
2.4 Middle of Line (MOL) DRAM Cell Transistor Process Flow.... 20
2.5 Summary................................................... 23

Chapter 3
Electrical Characterization of Carbon Implanted Into Drain of DRAM Cell Transistor............................................... 38
3.1 Introduction.............................................. 38
3.2 Carbon Implement DRAM Cell Transistor Drain Side Process.. 38
3.3 The Dosage of Carbon Implantation on DRAM Cell Transistor Drain......................................................... 39
3.4 Electrical Analysis of DRAM Cell Transistor with Carbon Implanted Drain............................................... 40
3.5 Summary................................................... 45

Chapter 4
CP Analysis of Carbon Implanted Into Drain of Cell Transistor For 256Mb DRAM.................................................... 78
4.1 Introduction.............................................. 78
4.2 DRAM Chip Probe Testing Flow.............................. 79
4.3 DRAM Chip Probe Testing Construction...................... 79
4.4 Chip Probe (CP) Analysis of DRAM Device with Carbon Implant Drain......................................................... 81
4.5 Characterization of Single Die Analysis of DRAM Device with Carbon Implant Drain.......................................... 83
4.6 Summary................................................... 84

Chapter 5
Conclusions................................................... 105





List of tables


Table 2-1. DRAM cell transistor main manufacturing flow………….…29
Table 2-2. DRAM cell transistor implant table………………………….37
Table 3-1. The split tables of carbon dosage are shown (a) the first and (b) the second experiment...………………………………………51
Table 3-2. The electrical data of linear region are by different carbon dosage. (a) the first and (b) the second experiment………….. 52
Table 3-3. The electrical data of saturation region are by different carbon dosage (a) the first and (b) the second experiment……………56
Table 3-4. Body effect of corner threshold voltage is by different carbon dosage at saturation. (a) the first and (b) the second experiment…………………………………………………….59
Table 3-5. The performance of bit line contact (CB) is by different carbon dosage at saturation. (a) the first and (b) the second experiment…………………………………………………….65
Table 3-6. The performance of junction and gate-induced-drain leakage (GIDL) is by different carbon dosage. (a) the first and (b) the second experiment…………………………………………….69
Table 3-7. Roll-off effect of channel threshold voltage is by different carbon dosage and channel length. (a) the first and (b) the second experiment……………………………………………75
Table 4-1. Chip probe (CP) and failure bin are by different carbon dosage. (a) the first and (b) the second experiment………………….89
Table 4-2. Failure bit count (FBC) of SUB VT failure bin sweep VBB voltage by different carbon dosage…………………………101
Table 4-3. Failure bit count (FBC) of SUB VT failure bin sweep VNWLL voltage by different carbon dosage..…………………………102
Table 4-4. Failure bit count of SWB failure bin sweep VPP voltage by different carbon dosage…...…………………………………103
Table 4-5. Failure bit count (FBC) of SWB failure bin sweep twr by different carbon dosage……………………………………104

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