臺灣博碩士論文加值系統

製程不斷的進步，連線的問題隨著製程的精進，顯得越來越重要。因應不斷浮現的問題，以及對於現象欲有更明確的了解；因此對於原本的問題，有更加深入了解的必要。對於一般連線方式，隨著製程進步，在連線上的實現，有其改良精進的空間。傳統連線上的方式已經行之有年，但為達成更佳的資源利用率和效能及功耗上的改善，傳統的連線方法已不再符合上述要求，而現今電路實現時，也需納入更多的限制，以確保不超出晶圓廠的製程。為了配合上述的問題，在此，基於之前研究的非均勻線寬結果，對於線寬限制的情形，有更清楚的研究跟討論。

本論文討論了當線寬在超出或不足於線寬限制時，非均勻線寬的連線要如何修正，才可以獲得較佳的結果。本論文提出的方式，對於具線寬限制之限制形線寬調整，有著明顯的改善，在利用Elmore Delay計算時間延遲上，接近於最佳非均勻線寬結果。對於現今可實現電路設計取向，提出了對稱型連線方案，以加入實際製作考量的方式，減少電路在晶體線路製作時，所可能受到的環境影響造成的誤差，及縮小不利因素所造成的影響，同時所提出的新連線形態，在不增加電路模擬時間的前提下，對於製作良率的增進，亦有一定的影響。

As fabrication process improves, the interconnection delay problem becomes more and more important. In order to solve this delay problem and understand the timing phenomenon more clearly at the same time, it is necessary for the timing delay to recognize more deeply the wire sizing problem. For a normal wire sizing implementation, some improvement may further be done. For the consideration of better resource usage and power / performance progress, conventional wire sizing does not meet the proposed requirement. Recently, circuit realization also needs to add more restricted conditions to satisfy foundry process. Based on the result of non-uniform wire sizing and the wire size constraints, constrained non-uniform wire sizing must be further studied.

This thesis discusses in detail how to adjust any non-uniform wire to get better result when wire size does not meet the wire constraints. The proposed methodology in this thesis has significance advance on constrained wire sizing. By applying an Elmore delay model to compute timing delay, an iterative approach is proposed to obtain a near-optimal constrained wire sizing for any wire. The experimental results show that our proposed approach obtains optimal non-uniform wire sizing. Because modern designs tend to design for manufacture (DFM), we suggest to use symmetric wire sizing and consider real physical design rules to reduce error rate when circuit layout implementation influences from environment effect and decreases other disadvantage factors.

目錄

摘要 ………………………………………………………………………………… I
Abstract ………………………………………………………………………… II
致謝 ……………………………………………………………………………… III
目錄 ………………………………………………………………………………… IV
圖表目錄 …………………………………………………………………………… VI
表格目錄 ………………………………………………………………………… VIII

1. 簡介 …………………………………………………………………………… 1
1.1 引言 …………………………………………………………………………… 1
1.2 實體設計流程……………………………………………………………………3
1.2.1 分割 ……………………………………………………………………4
1.2.2 版面規劃…………………………………………………………………4
1.2.3 繞線………………………………………………………………………5
1.3 連線上的問題……………………………………………………………………6
1.3.1 連線結構 …………………………………………………………………6
1.3.2 信號完整性………………………………………………………………8
1.3.3 製程導向設計……………………………………………………………10
1.3.4 線寬調整…………………………………………………………………11
2. 相關研究 ………………………………………………………………………16
2.1 Elmore延遲 ……………………………………………………………………16
2.2 相關論文…………………………………………………………………………20
2.2.1 多階層單一線段最佳線寬公式 …………………………………………21
2.2.2 非均勻線寬之時間延遲 …………………………………………………23
3. 研究動機與問題描述 ……………………………………………………………26
3.1 研究動機 …………………………………………………………………………26
3.2 問題描述 …………………………………………………………………………27
4. 非均勻線寬調整 …………………………………………………………………28
4.1 非均勻線寬調整演算法 …………………………………………………………28
5. 具限制之非均勻線寬調整演算法……………………………………………… 35
5.1 定義非均勻線寬………………………………………………………………… 35
5.2 一般非均勻線寬調整…………………………………………………………… 37
5.3 具有線寬限制的非均勻線寬調整 ………………………………………………38
5.3.1 僅考慮最小線寬限制之線寬調整 ………………………………………38
5.3.2 僅考慮最大線寬限制之線寬調整 ………………………………………40
5.3.3 同時考慮最小及最大線寬限制之線寬調整 ……………………………42
5.4 對稱形之非均勻線寬調整……………………………………………………… 45
5.4.1 非均勻線寬調整之分析………………………………………………… 45
5.4.2 實體製作的考慮………………………………………………………… 45
5.4.3 對稱型線寬調整 …………………………………………………………46
6. 實驗結果與結論 …………………………………………………………………48
6.1 實驗結果 …………………………………………………………………………48
6.2 結論 ………………………………………………………………………………51
參考文獻………………………………………………………………………………………52

參考文獻

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