一般理想的BGA構裝是四層板的結構，其構裝含有兩層的信號層及兩層的電源層(power/ground layer)，使整個構裝擁有較佳的電氣特性。然而二層基板因為擁有低成本的優勢，所以仍是BGA的主流產品，因此二層基板的電源結構值得深入探討。
因為二層板並沒有完整的電源層平面(power/ground plane)，所以其電源只能透過電源環(power/ground ring)及電源線(power trace)的佈局形式來傳遞。在這種情形下電源環及電源線的佈局設計方法，便會主宰電源的分佈特性。因為BGA佈局設計擁有很大的自由度，換句話說不同的人設計出來的結果都不會完全一樣。這造成設計上的多樣化，更產生在電源特性上難以捉摸的結果。
因此，有必要系統化的分析各式設計對電源分佈所產生的影響。因此本研究著重在BGA電源佈局設計對電源擾動的影響(The Power Disturbance Effect On BGA Due to The Power/Ground Layout Design)。

As the operating clock period of processor is becoming shorter, interconnections of packages can not be treated as ideal short circuits or lumped circuits anymore. For the requirement of using transmission-line theory to model interconnections, a CAD（PakSi-E）simulation tool will be needed in our research to extract the parasitic effect.
There is more freedom for BGA layout design than that for lead frame layout design. In other words, the substrate layouts with same specification designed by the different designers will show us a large difference due to their different design methodology. That‘s why it is difficult for different designers to produce an identical (or almost identical) layout design in order to get the same electrical performance.
The purpose of this research is to analyze various types of BGA layout designs and the most important is to understand the PI (Power Integrity) behavior due to the different Power/Ground layout patterns.

目 錄
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 ix
圖目錄 x
第1章 緒 論 1
1.1 研究背景與動機 1
1.2 研究目的 2
1.3 研究架構 6
第2章 電子封裝 8
2.1 電子封裝基本介紹 8
2.1.1 DIP元件 10
2.1.2 SIP元件 10
2.1.3 PGA元件 12
2.1.4 SOP元件 12
2.1.5 SOJ元件 12
2.1.6 PLCC元件 13
2.1.7 QFP元件 14
2.1.8 BGA元件 15
2.1.9 FC元件 16
2.2 BGA (BALL GRID ARRAY)介紹 17
2.2.1 BGA架構形式 18
2.2.2 BGA的分類 20
A. PBGA (Plastic BGA) 20
B. CBGA (Ceramic BGA) 21
C. TBGA (Tape BGA) 21
D. MBGA (Metal BGA) 23
2.2.3 BGA的優異性 24
2.2.4 技術趨勢和未來發展 25
2.3 基板 27
2.3.1 基板的材料 27
2.3.1.1 環氧樹脂(FR-4)基板 28
2.3.1.2 Cyanate ester (BT)基板 28
2.3.1.3 Aramid環氧基板 28
2.3.1.4 陶瓷蕊基板(Ceracom) 28
2.3.2 基板的特性與技術現況 29
第3章 PCB電性問題探討 32
3.1 信號完整性SI(SIGNAL INTEGRITY) 32
3.1.1 時序(Timing) 32
3.1.1.1 臨界位準(Threshold Level) 34
3.1.1.2 多層基板導通孔(Via Hole)之影響 36
3.1.1.3 其它雜訊的影響 37
A. 電磁雜訊(Electromagnetic Noise) 37
B. 天線(Antenna) 39
3.1.2 反射(Reflection) 40
3.1.2.1 反射之理論 40
3.1.2.2 反射及其產生之過程 42
3.1.2.3 終端技術 45
A. 並聯電阻 46
B. 戴維寧終端(Thevenin’s Termination) 48
C. AC並聯終端 49
D. 串聯終端 51
E. 二極體終端 52
3.1.2.4 無分岔配線(Daisy Chain) 53
3.1.3 串音(Crosstalk) 55
3.1.3.1 電容耦合雜訊 56
3.1.3.2 電感耦合雜訊 57
3.1.3.3 回返路徑(Return Path) 58
3.1.3.4 近端串音與遠端串音 60
3.1.3.5 減少串擾之方法 61
3.1.4 clock skew 64
3.1.4.1 電子元件的特性差異 64
A. 傳播延遲 64
B. 邏輯閘臨界電壓 65
C. 邊緣速率(edge rate) 65
3.1.4.2 佈線路徑的差異 66
A. 電容性負載變動 66
B. 傳播速率的變動 66
C. 蝕刻-幾何的變動 67
3.1.4.3 電路結構和設計方法的差異 67
3.1.4.4 其他參數的差異 67
3.2 電源完整性PI(POWER INTEGRITY) 68
3.2.1 電源分配系統 68
3.2.2 地電位彈跳(Ground Bounce) 68
3.2.3 傍路電容器(Bypass Condenser) 72
3.2.4 Swiss Cheese Effect與回返路徑(Return Path) 75
第4章 電子封裝之等效電路模型 78
4.1 基本概念 78
4.1.1 時域或頻域 78
4.1.2 高速數位的條件 79
4.1.3 四種電性等效模型 82
4.1.4 集總模型vs離散模型 88
4.1.5 互容(Mutual Capacitance)VS互感(Mutual Inductance) 88
A. 互容 88
B. 互感 91
4.2 傳輸線基本理論 93
4.2.1 傳輸線的定義 94
4.2.2 實際的傳輸線性質 95
4.2.3 微帶線和帶狀線特徵阻抗的計算 96
第5章 研究方法與模擬分析結果 98
5.1 研究方法與流程 98
5.1.1 Package模擬分析流程 98
5.1.2 PakSi-E 100
5.1.3 PakSi-E操作說明 101
5.1.4 PakSi-E電磁與電路能量的關係 104
5.2 模擬分析結果 109
5.2.1 Power/Ground Ring間距的影響 111
5.2.1.1 電源環(Power/Ground Ring) 111
5.2.1.2 電路模型(Circuit Model) 113
5.2.1.3 模擬分析(Simulation Analysis) 114
A. RLCG Extraction 115
B. 時域分析 118
5.2.2 DFGOc 119
5.2.3 DFPT 122
5.2.4 DFGOc-w03與DFPT-w03比較 123
5.2.5 BWP的比較 125
5.2.6 DFTP 128
5.2.7 DFTP頻率改變的比較 132
A. DFTPO00 改變頻率的結果 132
B. DFTPO01 改變頻率的結果 134
C. DFTPO03 改變頻率的結果 136
5.2.8 PGRWc 138
第6章 結論與願景 142
6.1 結論 142
6.2 願景 143
參考文獻 144
簡 歷 147

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