臺灣博碩士論文加值系統

IR-drop是超深次微米製程下的一個訊號整合議題。電壓降不只引起電路延遲，在低電壓供應時更會造成降低電路的雜訊容忍度的問題，而且電子遷移（Electromigration, EM）也會造成電路可信度的問題。
在此議題下，有兩個最大尖峰電流評估的理論被提出來。理論一是使用非相依性測試向量（Pattern Independent）的方式，這是被認定為最差情況（Worst-case）的一種理論。理論二是利用相依性測試向量（Pattern Dependent）的方式，這是較理論一實際的一種評估方式。
電路的實際尖峰電流可以由使用設計者所提供的驗證輸入測試向量中獲得。由於理論一的方式高估了尖峰電流，精確的尖峰電流是動態行為（與測試向量相依），所以使用真實的測試向量可以計算出真實的邏輯閘切換尖峰電流。這種量測方法精確且低於理論一的方法，可以更合理地幫助於電壓網絡設計。
傳統的靜態時序分析並沒有考慮不同的供應電壓情況下的延遲影響，及電壓降對邏輯閘延遲時間的改變，以一個簡單的例子只提供0.78VDD電壓源，所測量的電路延遲就比原先的時間多出14.7%，在這樣的考量下，所以我們發展最大尖峰電流計算與電壓降分析的架構，希望藉此分析了解電壓降影響下造成的電路延遲效應。
我們使用HSPICE正確萃取與校正標準元件中的庫特徵值，將資訊整理成電流、電壓、延遲時間的三種狀態關係表格，來計算最大尖峰電流與電壓降及延遲效應的分析架構，了解電路中嚴重電壓降所造成的電路延遲效應，最後利用餘裕時間來減少邏輯電路中的尖峰電流。

IR-drop is a well-known signal integrity issue in very deep submicron technology. The voltage drop does not only induce circuit delay but also reduce the circuit noise margin from lower supply voltage and bring reliability issue from electromigration. In this thesis, there are two maximum transition current estimation methods are discussed, Method-1 is pattern independent, which is worst-case predication. The Method-2 is pattern independent that more realistic than Method-1. The real circuit transition current could get by applying the verification input patterns provided by designer. Due to the peak current overestimated by using Method-1, and the accurate peak current is dynamic behavior（dependent on pattern）, so use real test bench could activate real gate transitions peak current. This measurement might lower and accurate than Method-1, could help reasonable power rail design. Traditional static timing analysis（STA） does not consider the different gate delay when occur varying supply voltage. We find a simple circuit’s delay increase up to 14.7% when voltage drop to 0.78Vdd. In this thesis, we propose a voltage aware delay calculation framework, which combine the peak current calculation and the path delay induced computation, the methodology will recompute the path delay, which take the voltage drop factors into consideration. The accurate（current, voltage, delay） library are characterized and calibrated by using SPICE. This proposed framework could analyze how serious of voltage drop from the circuit, and joint with the gate-sizing/input-reordering peak-current reduction techniques finally.

封面內頁
簽名頁
博碩士論文授權書 iii
中文摘要 iv
英文摘要 vi
誌謝 vii
目錄 viii
圖目錄 x
表目錄 xii

第1章 序論 1
1.1 研究動機 1
1.2 論文研究方向 2
1.3 論文研究重點 3
1.4 架構（Framework） 3
第2章 相關研究與背景知識 5
2.1 傳統的電路延遲計算技術 9
2.1.1 線性靜態時序分析（LSTA） 10
2.1.2 線性動態時序分析（LDTA） 12
2.2 新型的電路延遲計算技術 14
2.2.1 非線性靜態時序分析（NLSTA） 14
2.2.2 非線性動態時序分析（NLDTA） 20
第3章 尖峰電流限制下之電路延遲計算 21
3.1 尖峰電流限制下之電路延遲計算簡介 21
3.2 尖峰電流限制下之電路延遲計算 22
3.2.1 設計流程 22
3.2.2 相關定義 25
3.2.3 詳細電壓降分析技術 27
3.2.3.1 以非線性動態時序分析（NLDTA）方式計算電路延遲 27
3.2.3.2 尖峰電流的分析 36
3.2.3.3 電壓降的分析 37
3.3 電壓降分析之演算法 39
3.3.1 電路延遲評估程序 40
3.3.2 尖峰電流評估程序 42
3.3.3 電壓降評估程序 44
第4章 實驗結果 47
4.1 電路時序分析 47
4.2 電路尖峰電流分析 53
第5章 結論 58
參考文獻 59
附錄A 標準細胞元件庫之SIS模型 62
附錄B 標準細胞元件庫之SYNOPSYS模型 65
附錄C 標準細胞元件庫之SYNOPSYS模型之使用方式 82

[1]S. Chowdhury and J.S. Barkatullah, "Estimation of Maximum Currents in MOS IC Logic Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 6, pp. 642-654, June 1990.
[2]Harish Kirplani, Farid N. Najm, and Ibrahim N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14（8）:998 - 1012, August 1995.
[3]A. Krstic and K.-T. Cheng, "Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits", Proceedings of Design Automation Conference, pp. 383-388, June 1997.
[4]H. Kriplani, F. Najm, and I. Hajj, "Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 435-438, 1994.
[5]Y.-M. Jiang, A. Krstic and K.-T. Cheng, "Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs", International Symposium on Low Power Electronics and Design, pp. 233-238, 1998.
[6]T. Murayama, K. Ogawa, H. Yamaguchi, "Estimation of peak current through CMOS VLSI circuit supply lines", Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific , pp. 295 –298, 1999.
[7]P. Vanoostende, P. Six and H.J. de Man, "PRITI: estimation of maximal currents and current derivatives in complex CMOS circuits using activity waveforms", Proceedings of the European Design Automation Conference, pp. 347-353, 1993.
[8]Yi-Min Jiang, Kwang-Ting Cheng, and An-Chang Deng, “Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs”, Dept. of Electrical & Computer Engineering University of California, pp. 233-238, August 1998.
[9]Chuan-Yu Wang, and Kaushik Roy, “Maximization of Power Dissipation in Large CMOS Circuits Considering Spurious Transition”, Volume 47,Issues 4, Senior Member, IEEE, pp. 483-490, April 2000.
[10]An-Chang Deng, Yan-Chyuan Shiau Shiau, and Kou-Hung Loh, ”Time Domain Current Waveform Simulation of CMOS Circuits”, Department of Electrical Engineering Texas A&M University, pp. 208-211, November 1988.
[11]ZHU Ning, ZHOU Runde, YANG Xingzi, “Global approach for CMOS circuit optimization by transistor resizing”, Tsinghua University, Beijing 100084, China.
[12]P.Girard, C.landrault, S.Pravossoudovitch, D.Severac, ”A Gate Resizing Technique for High Reduction in Power Consumption”
[13]Jiong Luo and Niraj K. Jha, “Battery-Aware Static Scheduling for Distribution Real-Time Embedded System”, Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544
[14]Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits”, Prentice Hall Electronics and VLSI Series, Charles G. Sodini, Series Editor.
[15]Ching-Hwa Cheng, Yung-Hau Lai, Wei-Chih Shen, Wen-Jui Chang, “Peak Current Aware Static Re-Timing Analysis”, International SoC Design Conference, pp. 105-108, 2004.