臺灣博碩士論文加值系統

近年來，以高階語言的方式來做描述、合成與模擬電路是一個以然成型的趨勢。其中基於模型的設計環境(Model-based approach)由於可以容易地描述及模擬 DSP 系統. 所以常被採用來應付高複雜度及開發期愈來愈緊迫的產品設計要求.基於高階硬體描述語言的特性，我們希望將一些計算上的問題 (DSP Application domain)在經由有效的數學方式(MOC Model of computation)所描述出來後，能將之合成為硬體描述語言的程式，進而能幫助在硬體電路上的設計，以符合更佳的設計效果。在此論文中，我們是以二個基於模型的設計環境(Model-based approach) AccelChip和PeaCE來驗證 motion estimation (ME) 演算法。PeaCE的模型與 Simulink 有許多異曲同工的地方，是故, 我們領略到PeaCE 的好處在於其程式碼再用、模擬速度和debugging除錯能力。而 AccelChip 則在實作至FPGA 上有較佳的表現力。

In recent years, using Model-based approach is a new trend for circuit design。 Model-based approach can be used to describe, synthesize, and simulate hardware circuits.Base on the features of hardware description language，we hope to declare computation via efficiency Model of computation (MOC) , then synthesize to RTL code . By adopt such way which can help circuit design to achieve better design outcome.Our work will focus on demonstration and compare the Motion Estimation results implement by PeaCE VS. Accelchip。The models of PeaCE are pretty similar to the product of Simulink，hence，we recognized that the advantages of PeaCE including code reusing, simulation speed and the capability for debugging;and AccelChip has a better practicability for implement to FPGA。

中文摘要…………………………………………………………………………I

英文摘要…………………………………………………………………………II

圖目錄 …………………………………………………………………………V

表目錄 …………………………………………………………………………VII

第一章 緒論…………………………………………………………….………1

第一節研究動機…………………………………………………………1

第二節論文架構…………………………………………………………2

第二章 Ptolemy ,PeaCE & AccelChip 簡介…………………………………3

第一節 Ptolemy….…….………………………………………………3

第2-1-1 SDF model….……………………..…………….…….5

第二節 PeaCE簡介……………….…………………………………….7

第2-2-1 SPDF & FRDF model …………………..……………….10

第三節 AceelChip 簡介…………….…………………………………13

第四節 PeaCE、AccelChip與知名的 Tools ………..………………17

第2-4-1 PeaCE 與 Ptolemy II ………………………………..18

第2-4-2 PeaCE 、AccelChip與 Matlab / Simulink..……….19

第2-4-3 PeaCE 與 其他 CAD Tools………………………..……20

第三章 Motion Estimator 說明……………………….………………………21

第一節 MPEG 原理…..…………..……….……………………………21

第二節 移動估測及補償 ..……………………………………………24

第三節 區塊比對法則 (MBA) …………………….……………………26

第四節 Motion Estimator Unit 設計說明………………….….……29

第五節 Accelchip 的 Coding style ……………….….……31

第四章 Motion Estimator Unit 模擬結果 ……………….…………………34

第一節 模擬環境與模擬步驟…………………………………………….34

第二節 實作結果………………………………………………………….38

第4-2-1 PeaCE Vs. AccelChip實作結果.………………….…..38

第4-2-2 與 AccelChip 之比較結果.……………..…..………..40

第五章 未來展望 ……………………………………………………..…………41

參考文獻……………………………..…………….………………………….……43

致謝詞………..………………………………..……………………………………46

作者簡介……..………………………………..……………………………………47

[1] Chanik Park and Soonhoi Ha, "Hardware Synthesis from SPDF Representation for Multimedia Applications", 13th International Symposium on System Synthesis, Madrid, Spain September 2000 .

[2] R. Lauwereins, M. Engels, M. Ade and J. Peperstraete, "Grape-II: A system-level prototyping environment for DSP applications", IEEE Computer, vol. 28, no. 2, pp. 35-43, February, 1995.

[3] P. Banerjee et al, "MATCH: A MATLAB Compiler for Configurable Computing Systems," Technical Report, Center for Parallel and
Distributed Computing, Northwestern University, Aug. 1999, CPDC-TR-9908-013.

[4] PeaCE(Ptolemy extension as Codesign Environment) project homepage http://peace.snu.ac.kr/research/peace/

[5] J. T. Buck, S. Ha, E. A. Lee, and D. G. Messerschmitt. "Ptolemy: A framework for simulating and prototyping heterogeneous systems," International Journal of Computer Simulation, Vol. 4, pp. 155-182, April 1994.

[6 ] F. Balarin, et al., "Hardware-Software Co-Design of Embedded Systems: The Polis Approach" pp. 10-33, Kluwer Academic Publishers, 1997.

[7] Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima "Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems" In Proceedings of the Asia South Pacific Design Automation Conference, Kitakyushu, Japan, January 2003.

[8] Alberto Sangiovanni-Vincentelli , Grant Martin "Platform-Based Design and Software Design Methodology for Embedded Systems"IEEE Design & Test of Computers November-December 2001



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[9] Taming Heterogeneity-The Ptolemy Approach PROCEEDINGS OF THE IEEE, VOL. 91, NO. 1, JANUARY 2003

[10] Praveen K. Murthy, Etan G. Cohen, Steve Rowland "System Canvas_ A New Design Environment for Embedded DSP and Telecommunication Systems " 2001
[11] Edward A. Lee, "DESIGN METHODOLOGY FOR DSP" 2002

[12] Chanik Park, Jaewoong Chung and Soonhoi Ha, "Extended Synchronous Dataflow for Efficient DSP System Prototyping", Design Automation for Embedded Systems, Kluwer Academic Publishers Vol. 3 pp 295-322 March 2002

[13] Seongnam Kwon, Hyunuk Jung and Soonhoi Ha, "H.264 Decoder Algorithm Specification and Simulation in Simulink and PeaCE", in Proc. International SoC Design Conference pp 9-12 Oct. 25-26 2004

[14] AccelChip, Inc. www.accelchip.com.

[15] XilinxCorporation,Inc.,www.xilinx.com.

[16] 鍾國亮，"資料壓縮的原理與應用",全華,2004年

[17] 白執善編譯，"影像壓縮技術",全華,2004年

[18] 蒙以正，" Matlab入門與精進",儒林,2004年

[19] H.264/AVC Software Coordination http://iphome.hhi.de/suehring/tml/

[20] The Math Works,Inc .,Writing S-functions(Version5),2002

[21] 林建孟,"適用半像素移動估測單元之積體電路設計",中原大學電機工程學系碩士論文,2004年

[22] Wonyong Sung and Soonhoi Ha, "Memory Efficient Software Synthesis using Mixed Coding Style from Dataflow Graph," IEEE Transactions on VLSI Systems, Vol. 8, pp 522-526, October 2000


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[23] Hyunok Oh and Soonhoi Ha , " Memory-optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples , EURASIP Journal on Applied Signal Processing Special Issue on "Rapid
Prototyping of DSP Systems" , Volume 2003, Number 6, pp.514-529, 1 May 2003.

[24] Hyunok Oh and Soonhoi Ha , " Fractional Rate Dataflow Model and Efficient Code Synthesis for Multimedia Applications ", Languages, Compilers, and Tools for Embedded Systems (LCTES''02) and Software and Compilers for Embedded Systems (SCOPES''02) , Berlin, Germany, June 19-21, 2002.

[25] Hyunuk Jung, Kangnyoung Lee, and Soonhoi Ha, "Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design," IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 10, pp 423-428, August 2002

[26] MATLAB for Synthesis Style Guide, AccelChip, Inc.