本論文描述一個利用延遲鎖定迴路來實現可程式化時脈產生器。可程式化時脈產生器可以被應用在微處理機系統的時脈產生器上或無線通訊的頻率合成器，藉由數位控制可程式化時脈產生的機制可以被用來當作可以重覆使用的IP提供使用者自由的選擇。在SOC的趨勢下使用延遲鎖定迴路(Delay-Locked Loops；DLL) 比鎖相迴路(Phase- Locked Loops；PLL)更具廣泛的運用，主要原因是因為DLL提供較好的低抖動時脈和穩定系統且面積小的優勢。
提出新型的差動門檻觸發延遲元件電路可以在不消耗靜態功率下有互補的全擺幅輸出，且呈現小的延遲抖動進而降低時脈產生器倍頻訊號的抖動。
提出的環形邊缘頻率合成器可以在低電壓操作且擁有Rise/Fall time對稱性的性能同時可以彈性設計倍頻要求只要增加延遲元件的數目。使用多工器的設計技巧可以容易使多相位訊號的延遲路徑的負載達到平均，而提供時脈產生器有較低抖動的倍頻訊號和很廣的操作頻率。
提出的可程式化時脈產生器採用TSMC 0.18um 1P6M CMOS製程，佈局總面積為0.687mm2，應用頻率範圍可操作輸入頻率在68MHz~120MHz，輸出頻率為68MHz~720MHz，量測時脈產生器六倍頻的輸出訊號720MHz下的抖動，RMS jitter為14.82ps，peak-to-peak jitter為64ps。

In this work, a DLL-based programmable clock generator is presented. A DLL-based clock generator can be applied in computer system as a clock generator or radio communication as a clock synthesizer. The digitally programmable schemes are implemented to realize reusable silicon IP. A delay-locked loop (DLL) is more suitable than a phase-locked loop (PLL) as a clock multiplier. For the reason, the DLL can provide lower signals jitter, better stability system and smaller area.
A new threshold-trigger delay element with full swing complementary output signals will consume no dc power. It exhibits small delay peak-to-peak jitter resulting reduced output clock jitter in DLL-based clock generator.
A new circular edge combiner may operate at a low supply voltage and performs symmetrical rise and fall operation. The multiplication factor of the clock generator can be easily chosen with the increasing number of delay elements. A multiplexer is easily designed with balanced loading on all delay paths of multi-phase signals to reduce the output clock jitter. The output frequency is also enhanced.
The DLL-based programmable clock generator, implemented in CMOS 0.18-um single-poly six-metal process, occupies 0.687 mm2 of active area. It shows that the input and output frequency ranges are 68MHz~120MHz and 68MHz~720MHz, respectively. It performs 64ps peak-to-peak jitter and 14.82ps rms jitter at 720MHz output signal.

中文摘要…………………………………………………………………………….i
英文摘要……………………………………………………………………………..ii
誌謝…………………………………………………………………………………...iii
目錄……………………………………………………………………………...iv
表目錄……………………………………………………………………………...vi
圖目錄……………………………………………………………………………….vii

第一章　緒論
1.1 時脈產生器……………………………………………………….......………..1
1.2 鎖相迴路之應用………………………………………………………...……..2
1.2.1頻率合成器…………………………….………………………………..2
1.2.2時脈產生器…………………………….………………………………..3
1.2.3光碟機的應用……………………………….…………………………..4
1.3 研究動機…………………...…………………………………………………..4
1.4 論文組織…………………...…………………………………………………..5

第二章　傳統鎖相迴路
2.1 鎖相迴路………………...………………..……………………...…………….6
2.1.1 基本鎖相迴路操作原理……………………………..……………..…..6
2.1.2 鎖相迴路之線性分析……………………………………..……………8
2.2 類比式延遲鎖定迴路…………………...……………………..……………..10
2.2.1類比式延遲鎖定迴路操作原理……………………….……......10
2.2.2類比式延遲鎖定迴路線性分析…………………………12
2.3 抖動…………………...………………………...…………………...…....…..13
2.4傳統電壓控制延遲元件介紹……………………………………….......15
2.4.1 Differential symmetric load延遲元件…………………..15
2.4.2 Current-starved延遲元件……………………………………......…..18
2.4.3 Varactor type延遲元件………………………18
2.4.4 Shunt capacitor延遲元件…………….………..………………...…..19
2.5傳統延遲鎖定迴路時脈產生器的介紹…………………......……….………..19
2.5.1 延遲鎖定迴路和鎖相迴路的比較…………..………………...….....….19
2.5.2傳統延遲鎖定迴路時脈產生器的介紹………………..………….…..21
第三章 可程式化CMOS延遲鎖定迴路時脈產生器
3.1 相位頻率檢測器...…………………………..………..………...…….…...24
3.2 充放電幫浦&低通濾波器...…………………………………….…….....…..25
3.3 新型差動延遲元件電路...……………………………………….….…...…..27
3.4 MOS Varactor..………….…...……………………………………….….…....30
3.4.1 Diode Capacitor...……...………………………..……….……..30
3.4.2 MOS capacitances...………………………………………………...31
3.4.3 Inversion-Mode MOS Varactor……………….....31
3.4.4 Accumulation-Mode MOS Varactor………………......…..32
3.5電壓控制延遲線………………………………………....…………...…...…..33
3.6新型環形邊緣頻率合成器電路……………………………….….....….….....34
3.7可程式化電路………………………………………….………….....………..35

第四章 電路模擬和比較
4.1延遲元件的比較………………………………….…………......…...………..38
4.2邊緣頻率合成器的比較………………………………….………….....…......44
4.3提出的可程式化延遲鎖定時脈產生器Pre-simulation模擬…......…………..45
4.4提出的可程式化延遲鎖定時脈產生器Post-simulation模擬和Corner驗證..52

第五章　電路佈局與晶片量測
5.1可程式化時脈產生器電路佈局…………......………………………………..64
5.1.1 相位頻率檢測器(PFD)電路佈局…………......…………………..66
5.1.2 充放電幫浦(Charge pump)&低通濾波器(Low pass filter)電路佈局..67
5.1.3 電壓控制延遲線(VCDL)電路佈局………………….....………...69
5.1.4 緩衝器(Buffer)電路佈局…………......………………………..71
5.1.5 多工器(MUX)電路佈局…………......……………………….……..72
5.1.6 環形邊缘頻率合成器(Circular edge combiner)電路佈…....73
5.1.7 輸出緩衝器(Output buffers)電路佈局…………......………..74
5.1.8 防止靜電保護電路電路佈局…………………………….......…..76
5.1.9 振盪器(OSC)電路佈局…………..............................77
5.2 晶片量測………………………………………………………...……79
第六章　結論與未來研究方向
6.1 結論…………………………………………………………………...…90
6.2 未來研究方向……………………………………………………...…90

參考文獻…………………………………………………………………………91
簡歷………………………………………………………………………..…94
附件…………………………………………………………………………..95

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