本論文將一有限場的乘法器，經過外部的控制訊號及控制電路，將它設計成可調式有限場乘法器。本論文將就位元移位式(Bit Slice)演算法及心臟收縮式(Systolic)演算法，兩種不同的有限場乘法器演算法，來做為可調式有限場乘法器之基本架構，經過設計之後的單一有限場乘法器，可利用外部控制信號來選擇乘法器運算於 ，其中 為可運算之有限場範圍上限，若 =10，則該電路經重新控制之後，將可運算於 、 、 … 、 等有限場，而本論文是以 =4的情況作討論。
設計完成之後，將以硬體描述語言(Verilog–HDL)來驗證本論文，所提出的設計方法。

In this thesis, we designed finite field multipliers with various control circuit that make the parameter m be adjustable. We design the multipliers with Bit-slice and Systolic array algorithms respectively.
In these designs, we can adjust the parameter of to be less than upper limit, N, such as N = 10. By various control mechanisms, the multipliers can be operated as multipliers for . We illustrate the methods and results with the special case of in details. We also use verilog programming to verify the designs proposed in this thesis.

中文摘要.............................................................i
英文摘要............................................................ii
誌謝...............................................................iii
目錄................................................................iv
圖目錄..............................................................vi
表目錄.............................................................vii
第一章 緒論..........................................................1
1.1 研究動機與目的................................................1
1.2 論文組織......................................................2
1.3 工作環境......................................................3
第二章 基礎代數......................................................4
2.1 簡介..........................................................4
2.2 群............................................................4
2.3 環............................................................5
2.4 場............................................................7
2.5 有限場........................................................8
2.6 基本運算.....................................................10
第三章 乘法器演算法.................................................12
3.1 簡介.........................................................12
3.2 位元移位式演算法.............................................12
3.3 心臟收縮式演算法.............................................19
第四章 可調式有限場乘法器之架構設計與模擬...........................25
4.1 簡介.........................................................25
4.2 可調式有限場位元移位式乘法器.................................25
4.2.1 以位元移位式演算法設計之分析.............................25
4.2.2 以位元移位式演算法製作可調式有限場乘法器.................30
4.2.3 可調式位元移位有限場乘法器架構設計.......................38
4.3 可調式有限場心臟收縮式乘法器.................................42
4.3.1 以心臟收縮式演算法設計之分析.............................42
4.3.2 以心臟收縮式演算法製作可調式有限場乘法器.................47
4.3.2 可調式心臟收縮有限場乘法器架構設計.......................57
第五章 結論與未來展望...............................................59
5.1 結論.........................................................59
5.2 未來展望.....................................................60
參考文獻............................................................61
附錄
A.一般型位元移位式乘法器程式....................................64
B.可調式位元移位式乘法器程式....................................70
　　C.一般型心臟收縮式乘法器程式....................................81
D.可調式心臟收縮式乘法器程式....................................88

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