臺灣博碩士論文加值系統

摘要
目前無線區域網路的主流產品多遵循著使用由多載波調變演變而來的正交分頻多工傳輸技術802.11a/g標準協定，該協定最高可提供54Mbps的傳輸速率。
然而傳輸率的需求是不斷的提升，所以本論文我們針對Radix-2演算法提出一個高效率高速雙倍率管線式快速傅利葉/反快速傅利葉轉換架構，將其運用在未來Gbps之多輸入多輸出正交分頻多工的通訊系統中，該雙輸入架構藉由時程分割、硬體共享的方式可提供兩倍資料運算產量，使得管線式乘法器及其他處理單元的運用率達到100%，減少硬體兩倍輸入時增加的硬體成本，藉由操作頻率及硬體使用效率兩者的提升，本高效率高速雙倍率管線式快速傅利葉/反快速傅利葉轉換架構可以比傳統單輸入快速傅利葉/反快速傅利葉轉換架構在處理量大上十倍。
本硬體設計採用UMC 0.18m 1P6M CMOS 製程，雙輸入資料的寬度設為16位元，電路於83MHz的執行速度下功率消耗406mW，晶片面積1.21mm2。

Abstract
Currently, the most popular WLAN products are using 802.11 a/g standards with Orthogonal Frequency Division Multiplexing (OFDM) evolved from multi-carrier transmission technology. It can provide the transmission rate up to 54Mbps.
However, the requirement of higher transmission rate is always desired. In this thesis an efficient high speed double-rate pipelined fast fourier transform / inverse fast fourier transform (FFT/IFFT) architecture with radix-2 algorithm in this thesis is proposed for OFDM communication systems in the future Gbps muti-input muti-output (MIMO) WLAN. It doubles the throughput by using dual-input architecture with the concept of “process division” to share the hardware. Furthermore, it reduces the hardware cost of double-data inputs and makes the utilization rate of pipelined multipliers and the processing elements reaching 100%. The throughput of the efficient high speed double-rate pipelined FFT/IFFT architecture is ten times of the traditional architecture for single input by higher operation frequency and efficient utilization of the hardware.
The core size of the proposed architecture is 1.21mm2 with the power consumption of 406mW at clock of 83MHz for dual-path data inputs with 16-bit word length using UMC 0.18m 1P6M CMOS technology.

目錄

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xii


第一章 序論 1
1.1 背景 1
1.2 研究動機 2
1.3 研究方向 2
1.4 章節介紹 3

第二章 背景知識 4
2.1 IEEE 802.11無線區域網路簡介 4
2.1.1 何謂無線區域網路 4
2.1.2 820.11標準簡介 4
2.2正交分頻多工系統之簡介 8
2.3 IEEE 802.11 a傳送端結構 12
2.4多輸入、多輸出(MIMO)正交分頻多工系統簡介 15
2.5 FFT/IFFT結構與S/P、P/S單元 18

第三章 FFT/IFFT演算法 …………………………….... 20
3.1 Radix-2 FFT演算法 22
3.2 Radix-4 FFT演算法 26
3.3 Radix-2/4 FFT演算法 29
3.4 Radix-2/4/8 FFT演算法 31
3.5 FFT/IFFT演算法特性 34

第四章 電路架構 35
4.1單輸入單輸出通用型管線式快速傅利葉/反快速傅利葉轉換結構 36
4.1.1 Stage1 37
4.1.2 Stage 2 ~ Stage 6 46
4.2雙輸入雙輸出通用型管線式快速傅利葉/反快速傅利葉轉換結構 49
4.2.1 Stage1 51
4.2.2 Stage 2 ~ Stage 6 60
4.3高效率高速雙倍率管線式快速傅利葉/反快速傅利葉轉換結構 65
4.3.1 Radix-2演算法於電路上的的特性 65
4.3.2 Radix-2雙倍率管線式快速傅利葉/反快速傅利葉轉換結構改良過程 ..66
4.3.3 Radix-2高效率高速雙倍率管線式快速傅利葉/反快速傅利葉轉換六級結構 .. ....71
4.3.4複數乘法器的改進：管線化處理 72


第五章 模擬與效能比較 75
5.1 Radix-2單、雙輸入通用型、高速高效率型管線式快速傅利葉/反快速傅利葉轉換結構Cell-Based電路合成…………………………..……………………71
5.1.1 Radix-2單雙輸入通用型管線式快速傅利葉/反快速傅利葉轉換結構Cell-Based電路合成效能比較…………..…..…………………….……81
5.1.2 Radix-2 雙輸入通用型和高效率高速管線式快速傅利葉/反快速傅利葉轉換結構電路合成效能比較………………………………...…………87
5.2高效率高速管線式快速傅利葉/反傅利葉轉換結構邏輯閘層次（Gate level）的電路模擬…………… …..….. 91
5.3 量測Radix-2單雙輸入通用型管線式快速傅利葉/反快速傅利葉轉換結構FPGA量測………………………………………..……….………………….94
5.4電路硬體佈線…………………………………..………………….…………...99
5.5最終電路模擬效能比較………………..……………………………………..101

第六章 結論 102

附錄 .103

參考文獻 111

參考文獻

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