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研究生:沈聖智
研究生(外文):Sheng-Chih Shen
論文名稱:低成本記憶體內建式自我測試架構及其設計自動化
論文名稱(外文):A Low Cost Memory Built-in Self-Test Architecture and its Design Automation
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:67
中文關鍵詞:記憶體內建自我測試低成本測試
外文關鍵詞:Memory BISTLow CostTesting
相關次數:
  • 被引用被引用:0
  • 點閱點閱:313
  • 評分評分:
  • 下載下載:39
  • 收藏至我的研究室書目清單書目收藏:1
  在本論文中我們提出一個具有高速、高錯誤涵蓋率、低測試功率消耗以及低面積耗費特性的低成本記憶體內建自我測試架構。我們亦開發出一套低成本記憶體內建自我測試合成器以自動產生此低成本記憶體內建自我測試架構之自動化產生程式,因而可以減少人為錯誤發生的機會並且提升此一測試架構的生產率。
  此低成本記憶體內建自我測試架構可以支援同步靜態隨機存取記憶體、同步動態隨機存取記憶體以及雙倍資料速率同步靜態隨機存取記憶體之測試。本架構採用單一記憶體內建自我測試控制器平行測試多個記憶體因而使得面積耗費相當的小。在本論文中我們亦證明了本架構所消耗的平行測試時間為在僅使用單一一個測試向量產生器架構情況下的最低時間。本架構中採用一些特殊的設計技巧因而可以達到相當高的運算速度以支援全速測試。在考量測試功率消耗的情形下我們也可以根據記憶體測試排程結果產生其所需要的電路架構。另外,我們亦提出一個基於葛雷碼的位址信號產生器而可有效率的降低位置信號相關電路的功率消耗。最後,我們也可以很容易的將多個測試演算法同時實現在本架構中而可以達到最佳的測試涵蓋率。
  本低成本記憶體內建自我測試架構已經通過一系列智慧財產權資格規範而成為一個適合再度使用的設計。針對編碼部分,負責檢查設計資格的檢查軟體- nlint 顯示本低成本記憶體內建自我測試架構沒有任何的警告以及錯誤,此一結果說明了本架構的硬體描述語言具極佳之編碼樣式(coding style)。針對驗證部分,我們所設計的測試平台在描述以及分支部分的程式涵蓋率可以達到百分之百,而針對觸發部分的程式涵蓋率如果不包含常數宣告的部分也可以達到百分之百,此一結果可以保證我們驗證機制的品質。
  In this thesis, a low cost memory built-in self-test architecture called the LCBIST architecture which has the features of high speed, high fault coverage, low test power consumption, and low area overhead is proposed. A design automation tool called the LCBIST synthesizer that can synthesize the LCBIST architecture so as to reduce the human errors and increase the productivity is also developed.
  The LCBIST architecture can support the testing of the synchronous static RAM (SRAM), the synchronous dynamic RAM (SDRAM) and the double data rate SDRAM (DDR SDRAM). Multiple memories can be tested in parallel using a single controller and hence the test area overhead is small. We also prove that the test application time of this architecture in the parallel mode is the minimum when only a single test pattern generator is used. With some special design techniques, the LCBIST architecture can achieve a very high clock rate for the purpose of at-speed testing. To reduce the test power, the LCBIST synthesizer can also generate the BIST circuitry based on the memory test scheduling results. In addition, a Gray code based address generator that can effectively reduce the power consumption of the address signal related circuits is also developed. Finally, multiple algorithms can be easily implemented in the LCBIST architecture to achieve the best fault coverage.
  The LCBIST architecture has passed a set of IP qualification rules and is well suitable for a reusable design. For the coding part, the design rule checker, nlint, shows that our LCBIST architecture has no errors and no warnings, which indicates that the quality of the hardware description language (HDL) coding style is good enough. For the verification part, the code coverage of our test bench for the statement and branch tests are 100%, and that for the toggle test is 100% excepting for those constant value signals. Thus the quality of the verification procedure is also satisfactory.
Abstract
Chapter 1 Introduction …………………………………………… P1
1.1 Motivation ........................................................................................P1
1.2 Introduction of Thesis ........................................................................P2
1.3 Organization of Thesis ........................................................................P3
Chapter 2 Background and Previous Work ……………………. P5
2.1 Background ........................................................................................P5
2.1.1 Synchronous Memories Introduction ................................................P5
2.1.2 March Algorithms Integration Scheme ................................................P8
2.1.3 Gray Code Counter ........................................................................P9
2.1.4 Encoding Scheme for Commands ........................................................P9
2.2 Previous Work ................................................................................P11
2.2.1 BIST Architecture ................................................................................P11
2.2.2 Gray Code Counter ................................................................................P13
Chapter 3 Low Cost BIST Architecture ………………………… P15
3.1 Architecture Overview and Design Strategy ………………………....P15
3.1.1 LCBIST Architecture Overview ……………………………………P15
3.1.2 Design Strategy ……………………………………………………P18
3.2 Parallel Testing for Multiple Memories ………………………………P19
3.2.1 Parallel Test Scheme ………………………………………………P20
3.2.2 Memory Test Scheduling Constraints ………………………………P23
3.3 Test Instruction Generator …………………………………………P25
3.3.1 Single Algorithm Test Instruction Generator …………………………P26
3.3.2 Multiple Algorithms Test Instruction Generator ……………………P26
3.3.3 Integrated Test Instruction Generator ………………………………P27
3.4 Command Translator ………………………………………………P28
3.5 Physical Signal Generator …………………………………………P29
3.6 Address Generator ……………………………………………………P32
3.6.1 Requirements of the Address Generator ………………………………P32
3.6.2 Gray Code Based Address Generator ………………………………P33
3.7 Signal Distributor ……………………………………………………P37
Chapter 4 Design Automation …..………………………………….. P38
4.1 Design Automation Flow …………………………………………P38
4.2 Setup File …………………………………………………………P40
Chapter 5 Experimental Results ………………………………….. P43
5.1 Simulation and Verification Results ………………………………P43
5.2 Synthesis Results ……………………………………………………P46
Chapter 6 Conclusions …………………………………………… P50
Appendix ………………………………………………………………P53
References ………………………………………………………………P64
[1]The International Technology Roadmap for Semiconductors (ITRS) 2003: http://public.itrs.net/
[2]Shi-Yu Huang, Ding-Ming Kwai, and Chris Huang, “A BIST Architecture for At-Speed DRAM Testing,” Journal of the Chinese Institute of Electrical Engineering, Vol. 8, No. 4, pp. 387-394, Nov. 2001.
[3]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang, “A Programmable BIST Core for Embedded DRAM,” IEEE Transactions on Design and Test of Computers, Vol. 16, Issue 1, pp. 59-70, Jan. 1999.
[4] Chih-Wea Wang, Chi-Feng Wu, and Jin-Fu Li et al., “A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM,” Proceedings of 9th Asia Test Symposium, pp. 45-50, 2000.
[5] Chin-Tsung Mo, Chun-Len Lee, and Wen-Ching Wu, “A Self-Diagnostic BIST Memory Design Scheme,” Proceedings of Memory Technology, Design and Testing Workshop, pp. 7-9, 1994.
[6] http://www.samsung.com/Products/Semiconductor/DRAM/RDRAM/
[7]W. L. Wang, K. J. Lee, and J. F. Wang, “A Universal March Pattern Generator for Testing Embedded Memory Cores,” Proceedings of 12th Annual IEEE ASIC/SOC Conference, pp. 228-232, 1999.
[8]W. L. Wang, K. J. Lee, and J. F. Wang, “An On-Chip March Pattern Generator For Testing Embedded Memory Cores”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 5, pp. 730-735 , Oct. 2001.
[9] H. Koike, T. Takeshima, and M. Takeda, “A BIST Scheme Using Microprogram ROM for Large Capacity Memories,” Proceedings of International Test Conference, pp. 815-822, 1990.
[10] A. Benso, S. D. Carlo, G. D. Natale, P. Prinetto, and P. Torino, “A Programmable BIST Architecture for Clusters of Multiple-Port SRAMs,” Proceedings of International Test Conference, pp. 557-566, 2000.
[11] Kamran Zarrineh and Shambhu J. Upadhyaya, “On Programmable Memory Built-In Self Test Architecture,” Proceedings of Design, Automation and Test in Europe Conference, pp. 708-713, 1999.
[12]Ching-Hong Tsai and Cheng-Wen Wu, “Processor-Programmable Memory BIST for Bus-Connected Embedded Memories,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 325-330, 2001.
[13]B. H. Fang and N. Nicolici, “Power-Constrained Embedded Memory BIST Architecture,” Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003
[14]B. N. Dostie, A. Silburt, and V. K. Agarwal, “A Serial Interfacing Technique for Built-In and External Testing of Embedded Memories,” Proceedings of Custom Integrated Circuits Conference, pp. 22.2-1-22.2-5, 1989.
[15]M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital Systems Testing and Testable Design,” Computer Science Press, New York, 1990.
[16]Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” In Proc. IEEE VLSI Test Symp., pp. 4–9, 1993.
[17]A. Maheshwari, W. Burleson, R. Tessier, “Trading off reliability and power-consumption in ultra-low power systems,” Proceedings of International Symposium on Quality Electronic Design, pp. 361-366, 2002.
[18]Mehta H., Owens R.M. and Irwin M.J., “Some issues in gray code addressing,” in Proceedings of Sixth Great Lakes Symposium on VLSI, pp. 178 – 181, 1996.
[19]Y. W. Chang, “Design and Automatic Generation for Universal Memory Built-In Self-Test System,” Master Thesis, Dept. of E.E., NCKU, Taiwan, June 2004.
[20]John F. Wakerly “Digital Design: Principles and Practices,” Prentice Hall 2001.
[21]Ing. Ivo Viščor, “Gray counter in VHDL,” in Proceedings of the Student FEI 2000, Brno 2000, pp. 399-401, 2000.
[22]A. J. van de Goor, “Testing Semiconductor Memories, Theory and Practice,” Gouda, The Netherlands: ComTex, 1998.
[23]A. J. van de Goor, I. B. S. Tlili, and S. Handiousi, “Converting March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories,” Proc. Int’l Workshop on Memory Technology, Design and Testing, pp. 44-52, 1998.
[24]A. J. van de Goor and I. B. S. Tlili, “March Tests for Word-Oriented Memories,” Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 501-508, 1998.
[25]P1500 SECT Task Forces. IEEE P1500 Website: http://grouper.ieee.org/groups/1500/
[26]http://www.micron.com/
[27]C. F. Wu, C. T. Huang, K. L. Cheng, and C. W. Wu, “Fault Simulation and Test Algorithm Generation for Random Access Memories,” IEEE Trans. on CAD, Vol. 21, No. 4, pp. 480-490, April 2002.
[28]http://www.springsoft.com.tw/
[29]http://www.transeda.com/
[30]IP Qualification Alliance, “IP Qualification Guidelines,” http://www.taiwanipgateway.org/IPQ/index.jsp
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