臺灣博碩士論文加值系統

現今嵌入式系統越益發達，以致於特殊應用的處理器佔市場重要的一環，處理器設計中除了須有良好的效能與低功率之外，縮短開發處理器的時間也十分重要，因此我們需要一個可重定目標的平台來快速的開發並評估新開發的處理器，且其模型需能精準的描述出處理器的行為並產生有效率的模擬器，本論文使用了運算狀態機模型設計現今流行的超純量處理器，論文中提出了如何應用此模型來模型化超純量處理器，所產生的模擬器為時脈精準度的模擬器，能評估出執行一個程式的效能，以提供給硬體或軟體設計者一個良好的參考。

With the growth of the embedded system, the application-specific processor is an important port of the market. In designing a processor, in addition to have a good performance and low power consumption, it is also important to shorten the time-to-market. Therefore, we need a retargetable modeling framework to rapidly explore and evaluate a candidate processor. The modeling technique of the framework needs to accurately capture complex processor behaviors and generate efficient simulators. In this thesis, we apply the Operation State Machine (OSM) model to design a popular superscalar processor. We also explain how to use the OSM model to model a superscalar processor. The generated simulator is a cycle-accurate simulator that can provide performance metric. It can offer both hardware and software developers a good reference.

Chapter 1 Introduction...................................................1
Chapter 2 Micro-processor Modeling.......................................3
　2.1 Survey of Micro-processor Modeling Approaches.......................3
　　2.1.1 Accuracy Levels of Processor models.............................3
　　2.1.2 Microprocessor Simulator........................................6
　2.2 Analysis of high quality micro-architecture modeling................7
Chapter 3 Operation State Machine Model..................................9
　3.1 The Operation State Machine Model...................................9
　　3.1.1 The Operation Layer............................................10
　　3.1.2 The Hardware Layer.............................................11
　　3.1.3 Interaction Approaches in the OSM model........................11
　3.2 Scheduling in OSM Model............................................14
　　3.2.1 OSM Scheduler in Operation Level...............................15
　　3.2.2 DE Scheduler in Hardware Level.................................18
　3.3 Modeling of Common Processor Features..............................18
　3.4 Modeling Detail of 5 Stage Pipelined Processor.....................23
Chapter 4 Case Studies: Alpha 21264 Superscalar Processor Architecture..29
　4.1 Fetch Stage........................................................30
　　4.1.1 Branch Predictor...............................................32
　　4.1.2 Instruction Fetch Queue (IFQ)..................................38
　4.2 Renaming Stage.....................................................39
　4.3 Issue Stage........................................................41
　　4.3.1 Out-out-order execution........................................41
　　4.3.2 Scheduler – Out-of-Order Issue Queue..........................42
　4.4 Reorder Buffer.....................................................43
　4.5 Memory Unit........................................................43
　　4.5.1 Load/Store Queue...............................................44
　　4.5.2 Memory Dependence Prediction...................................46
Chapter 5 Alpha OSM Simulator and Simulation Results....................51
　5-1 Implementation Detail..............................................51
　5-2 Performance and Result.............................................61
　　5.2.1 Simulation Result..............................................61
Chapter 6 Conclusion...................................................64
Reference................................................................65

[1] Wei Qin and , Modeling and Description of Embedded Processors for the Development of Software Tools, Ph.D Thesis, Princeton University.
[2] Wei Qin and S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, IEEE/ACM Design Automation and Test in Europe, March 2003, pp. 556-561.
[3] Wei Qin, A Formal Concurrency Model Based Architecture Description Language for Synthesis of Software Development Tools, ACM 2004 Conference on Languages, Compilers, and Tools for Embedded Systems, June 2004, pp. 47-56.
[4] “Alpha Architecture Handbook,” Product #EC-QD2KC-TE, Compaq Computer Corporation, 1998
[5] “Alpha 21264/EV67 Microprocessor Hardware Reference Manual,” Compaq Computer Corporation, Product #DS–0028B–TE, 2000
[6] IVM – Verilog Alpha Processor, http://www.crhc.uiuc.edu/ACS/tools/ivm/install.html (current July 2005).
[7] George Z. Chrysos , Joel S. Emer, Memory dependence prediction using store sets,
Proceedings of the 25th annual international symposium on Computer architecture, p.142-153, June 27-July 02, 1998, Barcelona, Spain
[9] D. A. Patterson and J. L. Hennessy, “Computer Atchitecture a Quantitative Approach”, Third Edition, Morgan Kaufmann Publisher, 2003
[10] R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, March/April 1999.
[11] R. Kessler, 'The Alpha 21264 Microprocessor Architecture', white paper, Compaq web site, Jan 1999
[12] D.Leibholz and R.Razdan, "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor," Proc. IEEE Compcon 97, IEEE Computer Soc. Press, Los Alamitos, Calif., 1997, pp. 28-36.
[13] S. McFarling, “Combining Branch Predictors”, Technical Report TN-36, Digital Western Research Laboratory, June 1993.
[14] Pees, Stefan, Modeling Embedded Processors and Generating Fast Simulators Using
the Machine Description Language LISA, 2002
[15] Manish Vachharajani, Ph.D. Thesis: Microarchitecture Modeling for Design-space Exploration, November 2004