臺灣博碩士論文加值系統

摘要
影像數位化為將影像作分析、儲存、運算及傳播時最有效率的方法。影像感測器是影像數位化的前端系統，傳統的攝相系統採用CCD影像感測器單頻道類比輸出，再以單顆類比數位轉換器將類比訊號轉換為數位影像訊號；此架構在數位影像資料規格日益龐大的發展趨勢下，是有其速度上的限制；亦不適於應用為機械儀器之視覺系統應用上。由於CCD在製程上並不相容於CMOS製程，因此無法將周邊電路整合，此於高度集成化SOC趨勢發展下，更是對此系統不利之處，
本論文內容提供理論，設計與實作一內含 64 x 64 單顆像素面積8.05 x 8.05 um2之APS像素陣列、陣列輸出經由平行相關性雙取樣電路與平行處理12位元類比數位轉換器後輸出數位化影像，此設計可以提供達HDTV 1080p規格之高畫面更新率；周邊電路則包含帶差參考電壓電路提供四組對溫度不敏感之參考電壓，與時脈產生器產生控制晶片運作之時脈電路。本攝相單晶片系統晶片採用TSMC 0.18 CMOS RF-Mix signal 3.3V 1p6m製程，單顆CDS佈局面積2042 um2，單顆ADC佈局面積 11254 um2 ENOB大於 11-bit，全晶片消耗功率小於90 mW，64 x64像素陣列循序掃瞄畫面更新率達520 Frame/s。

ABSTRACT
Images in digital format is more convenient for analysis, storage, and operation. In order to achieve the function of digital image output, modern imaging systems are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signal to digital format. However, this traditional architecture faces the insufficient frame-rate limitation as high quality, high resolution digital images are required. For some machine vision applications this architecture cannot achieve the desirable speed. Modern trend on implementing imagers, ADC and other peripheral circuits on a single chip with CMOS process provides an alternative solution.
This thesis describes the theory, design, and characterization of a prototype 64 x 64 APS pixel array. Area for each pixel is 8.05 x 8.05 um2. The array output utilizes a column-parallel correlated double sampling circuit, and a column-parallel 12-bit analog-to-digital converter to convert image signal to digitized format. It allows a high frame rate that can achieve the HDTV 1080p specification. A bandgap reference voltage circuit provides four temperature insensitive reference voltages. An on-chip clock generator generates all operation signals to control the chip. This camera-on-a-chip system uses TSMC 0.18 CMOS RF-Mix signal 3.3V 1p6m process. The layout area of the CDS is 2042 um2. And the ADC area is 11254 um2 with ENOB as high as 11-bit. The power consumption of the chip is 87 mW . The frame rate of the 64x64 CMOS image sensor array can achieve 520 Frames/s with progressive scan.

目錄
第一章 簡介.......................................1
1.1 研究動機......................................1
1.2 晶片規格......................................5
1.2.1 晶片規格設計................................5
1.2.2 近期研究發展現況與晶片規格表................6
第二章 背景資料...................................8
2.1 CCD及CMOS影像感測器介紹.......................8
2.1.1 CCD影像感測器...............................8
2.1.2 CMOS影像感測器.............................12
2.1.3 CCD與?CMOS影像感測器之比較.................14
2.2 交換電容式電路...............................15
2.2.1 採樣開關...................................17
2.2.2 速度考量...................................18
2.2.3 精確度考量.................................20
2.3 運算放大器...................................22
2.3.1 運算放大器型態.............................22
2.3.2 共模迴授電路...............................28
2.4 類比數位轉換器型態...........................28
2.4.1 Delta?Sigma?式.............................29
2.4.2 快閃式.....................................30
2.4.3 雙斜率式...................................31
2.4.4 運算式.....................................32
第三章 晶片之架構及設計..........................34
3.1 全晶片架構...................................34
3.2 像素陣列（Pixel?Array）及控制電路............35
3.2.1電路架構及運作原理..........................35
3.2.2非理想特性..................................39
3.2.3像素陣列之模擬結果與佈局圖..................42
3.2.4像素陣列之控制電路..........................43
3.3 運算放大器電路及設計.........................44
3.3.1運算放大器之共模迴授電路....................47
3.3.2運算放大器非理想性分析......................49
3.3.3任意雜訊....................................51
3.4 相關性雙取樣電路.............................53
3.4.1 電路與運作原理.............................53
3.4.2 理想狀態之操作模式分析.....................55
3.4.3 CDS之非理想特性............................57
3.4.4 CDS運算放大器模擬結果......................62
3.4.5 CDS模擬結果................................64
3.4.6 CDS佈局圖..................................66
3.5 遞迴式數位類比轉換器.........................67
3.5.1 遞迴式類比數位轉換器之狀態分析.............70
3.5.2 遞迴式類比數位轉換器非理想性分析...........73
3.5.3 遞迴式類比數位轉換器模擬結果...............81
3.6 帶差參考電路.................................84
3.7 時脈產生器...................................89
3.7.1 時脈產生前置放大器.........................90
3.7.2 邏輯電路...................................92
第四章 測試......................................95
4.1 測試架構.....................................95
4.2 測試驗證平台.................................95
4.3 類比數位轉換器...............................98
4.4 相關性雙取樣電路及類比數位轉換器............101
4.5 單晶片攝相系統測試..........................101
第五章 結論.....................................102
5.1 論文貢獻....................................102
5.2 未來改善....................................102
Reference.......................................103

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