臺灣博碩士論文加值系統

　　本論文主旨在實現H.264影像系統中的去區塊濾波器。我們提出一個全新的像素資料排列方法，針對影像中的像素資料作特殊方式的排列，藉由像素資料的特殊排列可以減少一塊轉置記憶體的使用；而因為像素資料不須經由轉置方向的程序就可以做垂直方向的濾波，所以我們更可以減少所需的工作週期。另一方面，我們也使用了四種不同的傳輸模式來傳送所需要的像素資料，由於這四種傳輸模式的使用，因此避免傳送不必要的資料，因此我們可以節省頻寬的使用；同時也減少了傳送像素資料的週期以及作濾波的工作週期。此架構比一般沒有經過特殊資料排列方式的去區塊濾波器能夠達到更高的輸出率但卻只需要較小的面積來實現。此架構利用UMC 0.18 �慆的製程技術合成，其合成的結果顯示，在時脈速度為66 MHz的情況下，所提出的去區塊濾波器架構能夠處理解析度為1280×720的影像。

　　This thesis focuses on the efficient implementation of the in-loop de-blocking filter for H.264 video coding systems. We propose a novel data arrangement style called Group-of-Pixel (GOP) for arranging the pixel data stored in the on-chip memory. With the pixel data arranged in the special way, we can avoid using the transpose memory that is usually used for vertical filtering. Since we do not have to transpose the directions of the pixel data, we can greatly reduce the working cycles for vertical filtering. In addition, we use four kinds of transmission modes to prevent from transferring the redundant pixel data into the on-chip memory. This will decrease the working cycles and also save the bandwidth. Therefore, the proposed architectures could provide higher throughput rate but realize in a smaller chip area than the de-blocking filter without special data arrangement method. The proposed architecture is synthesized with UMC 0.18 �慆 technology. The synthesized in-loop de-blocking filter architecture could process video in 720p HD (1280×720) format at 66 MHz.

Table of Contents i
Acknowledgement ii
List of Figures iii
List of Tables v
Abstract vii
Chapter 1 Introduction 1
　1.1 Motivation 1
　1.2 Organization of the Thesis 3
Chapter 2 Basic Concepts for Video Coding and the Classification of 　　　　　　　　　　De-blocking Filters 5
　2.1 Basic Concepts for Video Coding 5
　2.2 What is Blocking Artifact? 10
　2.3 Difference between Post Filtering and In-loop Filtering 11
　2.4 The H.264 Video CODEC 15
Chapter 3 The Algorithm of H.264/AVC In-loop De-blocking Filter 18
　3.1 Boundary Analysis 18
　3.2 Filtering 26
Chapter 4 Design of H.264/AVC In-loop De-blocking Filter 32
　4.1 Real-time Requirements for Various Resolutions 32
　4.2 Overview of Proposed Architecture 33
　4.3 On-chip Memory Organization 35
　4.4 Four Modes for Transferring Data 43
　4.5 One-D Filter Architecture 45
Chapter 5 Synthesis Results and Verification 47
　5.1 Synthesis Results 47
　5.2 Verification 48
　　5.2.1 Verification Environment 48
　　5.2.2 RAM-based Interface Connection 49
　　5.2.3 Simulations 51
　5.3 Summary 54
Chapter 6 Conclusions and Future Work 55
　6.1 Conclusions 55
　6.2 Future Work 56
References 57

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