臺灣博碩士論文加值系統

　　鎖相迴路被廣泛的應用在晶片上需要精確時間的高性能數位系統上。特別是當操作頻率變快，這些系統的性能會受到時間上的抖動或者是相位的雜訊影響。鎖相迴路中的壓控震盪器容易受到來自供應電壓源的雜訊所影響，而這些雜訊是來自數位電路開關時造成的。
　　從系統的角度來看，這份研究深入探討鎖相迴路的參數所帶來的影響，例如頻寬以及頻率響應時的平坦度。這份分析考慮了幾個在鎖相迴路中的幾個常見的雜訊來源，並直觀地導出如何選擇最佳的迴路參數以獲得最少的時間抖動。
　　在電路的角度來看，我們實現了兩種不同架構的壓控震盪器。一個採用較為簡單的電壓轉電流的架構，但使用了雜訊濾除的機制。另外一個壓控震盪器使用自我偏壓的運算放大器以達到較好的線性度以及抗雜訊的能力。我們用自我偏壓的壓控震盪器，以及我們所提出的電流幫浦實現寬頻率範圍的鎖相迴路，並同時對整個鎖相迴路系統進行最佳化。

　Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. Any timing jitter or phase noise significantly degrades the performance of these systems, especially as operating frequency increases. Switching activity in large digital systems introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL, especially the voltage-controlled oscillators (VCOs),
　At system level, this work investigates the effects of PLL design parameters, such as bandwidth and peaking in frequency response, on timing jitter of PLL output clock. The analysis includes several common noise sources in a PLL and develops an intuition for selection design parameters to obtain minimum output jitter based on the dominant noise source.
　At circuit level, two different architectures of VCOs are realized. One employs simple V-I but with noise-canceling techniques. And the other VCO using an operational amplifier, which is self-biased, to maintain good linearity and sensitivity of VCO. The self-biased VCO is used for designing a wide frequency range PLL, with a proposed charge pump. Also, the loop parameters of the PLL are well chosen in the design process.

TABLE OF CONTENTS

CHAPTER PAGE
CHAPTER 1. INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3
CHAPTER 2. FUNDAMENTALS OF PLLS 5
2.1 Definition of PLLs 5
2.2 Components of PLLs 6
2.2.1 Voltage-Controlled Oscillator (VCO) 7
2.2.2 Phase Detector or Phase Frequency Detector 9
2.2.3 Charge-pump and Loop filter 12
2.3 Applications of PLLs 13
2.3.1 High-Speed Serial Link 13
2.3.2 Fractional-N Synthesizer 14
2.4 Delay-Locked Loops 15
CHAPTER 3. THEORY AND JITTER ANALYSIS OF PLLS 16
3.1 Loop Characteristics 16
3.1.1 Second Order Systems 16
3.1.2 S-domain Model of PLLs 21
3.2 Definitions of Jitter 25
3.3 Jitter in Ring Oscillators 26
3.4 Noise Sources of PLL 28
3.5 Jitter Optimization of PLL 31
3.5.1 PLL Noise Transfer Function 31
3.5.2 Jitter due to VCO Noise 33
3.5.3 Jitter due to Input Clock Noise 35
CHAPTER 4. DESIGN AND SIMULATION OF A LOW-JITTER PLL 38
4.1 Design Consideration 38
4.2 Design of VCO 40
4.2.1 A VCO with Simple Noise Canceling Technique 41
4.2.2 A self-biased VCO 43
4.3 Design of Charge-Pump and Loop Filter 49
4.4 Design of PFD and Frequency Divider 51
4.5 Simulation and Discussion 53
4.6 Proposed VCO Architecture 59
CHAPTER 5. CONCLUSIONS AND FUTURE WORK 64
REFERENCE 66

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